Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) // Copyright (C) 2008-2017 Andes Technology Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/printk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <asm/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <nds32_intrinsic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) unsigned int resume_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) unsigned int *phy_addr_sp_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static void nds32_suspend2ram(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	pgd_t *pgdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	p4d_t *p4dv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	pud_t *pudv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	pmd_t *pmdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	pte_t *ptev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	pgdv = (pgd_t *)__va((__nds32__mfsr(NDS32_SR_L1_PPTB) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		L1_PPTB_mskBASE)) + pgd_index((unsigned int)cpu_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	p4dv = p4d_offset(pgdv, (unsigned int)cpu_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	pudv = pud_offset(p4dv, (unsigned int)cpu_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	pmdv = pmd_offset(pudv, (unsigned int)cpu_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	ptev = pte_offset_map(pmdv, (unsigned int)cpu_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	resume_addr = ((*ptev) & TLB_DATA_mskPPN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 			| ((unsigned int)cpu_resume & 0x00000fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	suspend2ram();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void nds32_suspend_cpu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	while (!(__nds32__mfsr(NDS32_SR_INT_PEND) & wake_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		__asm__ volatile ("standby no_wake_grant\n\t");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int nds32_pm_valid(suspend_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	case PM_SUSPEND_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	case PM_SUSPEND_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	case PM_SUSPEND_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int nds32_pm_enter(suspend_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	pr_debug("%s:state:%d\n", __func__, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	case PM_SUSPEND_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		nds32_suspend_cpu();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	case PM_SUSPEND_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		nds32_suspend2ram();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static const struct platform_suspend_ops nds32_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	.valid = nds32_pm_valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	.enter = nds32_pm_enter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int __init nds32_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	pr_debug("Enter %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	suspend_set_ops(&nds32_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) late_initcall(nds32_pm_init);