^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (C) 2005-2017 Andes Technology Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define OF_DT_MAGIC 0xd00dfeed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define OF_DT_MAGIC 0xedfe0dd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) .globl swapper_pg_dir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .equ swapper_pg_dir, TEXTADDR - 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Kernel startup entry point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .section ".head.text", "ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .type _stext, %function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ENTRY(_stext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) setgie.d ! Disable interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Disable I/D-cache and enable it at a proper time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) mfsr $r0, $mr8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) li $r1, #~(CACHE_CTL_mskIC_EN|CACHE_CTL_mskDC_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) and $r0, $r0, $r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) mtsr $r0, $mr8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Process device tree blob
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) andi $r0,$r2,#0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) li $r10, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) bne $r0, $r10, _nodtb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) lwi $r0, [$r2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) li $r1, OF_DT_MAGIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) bne $r0, $r1, _nodtb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) move $r10, $r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) _nodtb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Create a temporary mapping area for booting, before start_kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) sethi $r4, hi20(swapper_pg_dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) li $p0, (PAGE_OFFSET - PHYS_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) sub $r4, $r4, $p0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) tlbop FlushAll ! invalidate TLB\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) mtsr $r4, $L1_PPTB ! load page table pointer\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #ifdef CONFIG_CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MMU_CTL_NTCC MMU_CTL_CACHEABLE_NON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MMU_CTL_NTCC MMU_CTL_CACHEABLE_WT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MMU_CTL_NTCC MMU_CTL_CACHEABLE_WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* set NTC cacheability, mutliple page size in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) mfsr $r3, $MMU_CTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #if CONFIG_MEMORY_START >= 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ori $r3, $r3, (MMU_CTL_NTCC << MMU_CTL_offNTC3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #elif CONFIG_MEMORY_START >= 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ori $r3, $r3, (MMU_CTL_NTCC << MMU_CTL_offNTC2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #elif CONFIG_MEMORY_START >= 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ori $r3, $r3, (MMU_CTL_NTCC << MMU_CTL_offNTC1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ori $r3, $r3, (MMU_CTL_NTCC << MMU_CTL_offNTC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #ifdef CONFIG_ANDES_PAGE_SIZE_4KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ori $r3, $r3, #(MMU_CTL_mskMPZIU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ori $r3, $r3, #(MMU_CTL_mskMPZIU|MMU_CTL_D8KB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #ifdef CONFIG_HW_SUPPORT_UNALIGNMENT_ACCESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) li $r0, #MMU_CTL_UNA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) or $r3, $r3, $r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mtsr $r3, $MMU_CTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* set page size and size of kernel image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) mfsr $r0, $MMU_CFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) srli $r3, $r0, MMU_CFG_offfEPSZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) zeb $r3, $r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) bnez $r3, _extra_page_size_support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #ifdef CONFIG_ANDES_PAGE_SIZE_4KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) li $r5, #SZ_4K ! Use 4KB page size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) li $r5, #SZ_8K ! Use 8KB page size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) li $r3, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) mtsr $r3, $TLB_MISC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) b _image_size_check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) _extra_page_size_support: ! Use epzs pages size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) clz $r6, $r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) subri $r2, $r6, #31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) li $r3, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) sll $r3, $r3, $r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* MMU_CFG.EPSZ value -> meaning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) mul $r5, $r3, $r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) slli $r5, $r5, #14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* MMU_CFG.EPSZ -> TLB_MISC.ACC_PSZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) addi $r3, $r2, #0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) mtsr $r3, $TLB_MISC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) _image_size_check:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* calculate the image maximum size accepted by TLB config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) andi $r6, $r0, MMU_CFG_mskTBW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) andi $r0, $r0, MMU_CFG_mskTBS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) srli $r6, $r6, MMU_CFG_offTBW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) srli $r0, $r0, MMU_CFG_offTBS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) addi $r6, $r6, #0x1 ! MMU_CFG.TBW value -> meaning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) addi $r0, $r0, #0x2 ! MMU_CFG.TBS value -> meaning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) sll $r0, $r6, $r0 ! entries = k-way * n-set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) mul $r6, $r0, $r5 ! max size = entries * page size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* check kernel image size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) la $r3, (_end - PAGE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) bgt $r3, $r6, __error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) li $r2, #(PHYS_OFFSET + TLB_DATA_kernel_text_attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) li $r3, PAGE_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) add $r6, $r6, $r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) _tlb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) mtsr $r3, $TLB_VPN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) tlbop $r2, RWR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) add $r3, $r3, $r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) add $r2, $r2, $r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) bgt $r6, $r3, _tlb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) mfsr $r3, $TLB_MISC ! setup access page size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) li $r2, #~0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) and $r3, $r3, $r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #ifdef CONFIG_ANDES_PAGE_SIZE_8KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ori $r3, $r3, #0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) mtsr $r3, $TLB_MISC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mfsr $r0, $MISC_CTL ! Enable BTB, RTP, shadow sp, and HW_PRE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ori $r0, $r0, #MISC_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) mtsr $r0, $MISC_CTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) mfsr $p1, $PSW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) li $r15, #~PSW_clr ! clear WBNA|DME|IME|DT|IT|POM|INTL|GIE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) and $p1, $p1, $r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ori $p1, $p1, #PSW_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) mtsr $p1, $IPSW ! when iret, it will automatically enable MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) la $lp, __mmap_switched
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) mtsr $lp, $IPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) iret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .type __switch_data, %object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) __switch_data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .long __bss_start ! $r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .long _end ! $r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .long __atags_pointer ! $atag_pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .long init_task ! $r9, move to $r25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .long init_thread_union + THREAD_SIZE ! $sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * The following fragment of code is executed with the MMU on in MMU mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * and uses absolute addresses; this is not position independent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .type __mmap_switched, %function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) __mmap_switched:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) la $r3, __switch_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) lmw.bim $r6, [$r3], $r9, #0b0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) move $r25, $r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) move $fp, #0 ! Clear BSS (and zero $fp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) beq $r7, $r6, _RRT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 1: swi.bi $fp, [$r6], #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) bne $r7, $r6, 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) swi $r10, [$r8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) _RRT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) b start_kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) __error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) b __error
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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