Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) // Copyright (C) 2005-2017 Andes Technology Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <linux/cacheinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) static void ci_leaf_init(struct cacheinfo *this_leaf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 			 enum cache_type type, unsigned int level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	char cache_type = (type & CACHE_TYPE_INST ? ICACHE : DCACHE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	this_leaf->level = level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	this_leaf->type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	this_leaf->coherency_line_size = CACHE_LINE_SIZE(cache_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	this_leaf->number_of_sets = CACHE_SET(cache_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	this_leaf->ways_of_associativity = CACHE_WAY(cache_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	this_leaf->size = this_leaf->number_of_sets *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	    this_leaf->coherency_line_size * this_leaf->ways_of_associativity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #if defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	this_leaf->attributes = CACHE_WRITE_THROUGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	this_leaf->attributes = CACHE_WRITE_BACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) int init_cache_level(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	/* Only 1 level and I/D cache seperate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	this_cpu_ci->num_levels = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	this_cpu_ci->num_leaves = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int populate_cache_leaves(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	unsigned int level, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	struct cacheinfo *this_leaf = this_cpu_ci->info_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	for (idx = 0, level = 1; level <= this_cpu_ci->num_levels &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	     idx < this_cpu_ci->num_leaves; idx++, level++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }