^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (C) 2005-2018 Andes Technology Corporation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <asm/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define _FP_W_TYPE_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _FP_W_TYPE unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _FP_WS_TYPE signed long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _FP_I_TYPE long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define _FP_MUL_MEAT_S(R, X, Y) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S, R, X, Y, umul_ppmm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define _FP_MUL_MEAT_D(R, X, Y) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D, R, X, Y, umul_ppmm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define _FP_MUL_MEAT_Q(R, X, Y) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q, R, X, Y, umul_ppmm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define _FP_MUL_MEAT_DW_S(R, X, Y) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) _FP_MUL_MEAT_DW_1_wide(_FP_WFRACBITS_S, R, X, Y, umul_ppmm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define _FP_MUL_MEAT_DW_D(R, X, Y) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) _FP_MUL_MEAT_DW_2_wide(_FP_WFRACBITS_D, R, X, Y, umul_ppmm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define _FP_DIV_MEAT_S(R, X, Y) _FP_DIV_MEAT_1_udiv_norm(S, R, X, Y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define _FP_DIV_MEAT_D(R, X, Y) _FP_DIV_MEAT_2_udiv(D, R, X, Y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define _FP_NANSIGN_S 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define _FP_NANSIGN_D 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define _FP_NANSIGN_Q 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define _FP_KEEPNANFRACP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define _FP_QNANNEGATEDP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) && !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs)) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) R##_s = Y##_s; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) _FP_FRAC_COPY_##wc(R, Y); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) } else { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) R##_s = X##_s; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) _FP_FRAC_COPY_##wc(R, X); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) R##_c = FP_CLS_NAN; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define __FPU_FPCSR (current->thread.fpu.fpcsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Obtain the current rounding mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define FP_ROUNDMODE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) __FPU_FPCSR & FPCSR_mskRM; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define FP_RND_NEAREST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define FP_RND_PINF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define FP_RND_MINF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define FP_RND_ZERO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define FP_EX_INVALID FPCSR_mskIVO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define FP_EX_DIVZERO FPCSR_mskDBZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define FP_EX_OVERFLOW FPCSR_mskOVF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define FP_EX_UNDERFLOW FPCSR_mskUDF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define FP_EX_INEXACT FPCSR_mskIEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SF_CEQ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SF_CLT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SF_CGT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SF_CUN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #ifdef __BIG_ENDIAN__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define __BYTE_ORDER __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define __LITTLE_ENDIAN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define __BYTE_ORDER __LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define __BIG_ENDIAN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define abort() do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define umul_ppmm(w1, w0, u, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) UWtype __x0, __x1, __x2, __x3; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) UHWtype __ul, __vl, __uh, __vh; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) __ul = __ll_lowpart(u); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) __uh = __ll_highpart(u); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) __vl = __ll_lowpart(v); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __vh = __ll_highpart(v); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) __x0 = (UWtype) __ul * __vl; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __x1 = (UWtype) __ul * __vh; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __x2 = (UWtype) __uh * __vl; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) __x3 = (UWtype) __uh * __vh; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) __x1 += __ll_highpart(__x0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) __x1 += __x2; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (__x1 < __x2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __x3 += __ll_B; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) (w1) = __x3 + __ll_highpart(__x1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) (w0) = __ll_lowpart(__x1) * __ll_B + __ll_lowpart(__x0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) UWtype __x; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) __x = (al) + (bl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) (sh) = (ah) + (bh) + (__x < (al)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) (sl) = __x; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) UWtype __x; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) __x = (al) - (bl); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) (sh) = (ah) - (bh) - (__x > (al)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) (sl) = __x; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define udiv_qrnnd(q, r, n1, n0, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) UWtype __d1, __d0, __q1, __q0, __r1, __r0, __m; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) __d1 = __ll_highpart(d); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) __d0 = __ll_lowpart(d); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) __r1 = (n1) % __d1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) __q1 = (n1) / __d1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) __m = (UWtype) __q1 * __d0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) __r1 = __r1 * __ll_B | __ll_highpart(n0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (__r1 < __m) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) __q1--, __r1 += (d); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (__r1 >= (d)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (__r1 < __m) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) __q1--, __r1 += (d); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) __r1 -= __m; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) __r0 = __r1 % __d1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) __q0 = __r1 / __d1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) __m = (UWtype) __q0 * __d0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) __r0 = __r0 * __ll_B | __ll_lowpart(n0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (__r0 < __m) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) __q0--, __r0 += (d); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (__r0 >= (d)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (__r0 < __m) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) __q0--, __r0 += (d); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) __r0 -= __m; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) (q) = (UWtype) __q1 * __ll_B | __q0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) (r) = __r0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) } while (0)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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