Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* Copyright (C) 2008-2018 Andes Technology Corporation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #ifndef __ASM_PMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #define __ASM_PMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <asm/unistd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <asm/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) /* Has special meaning for perf core implementation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define HW_OP_UNSUPPORTED		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define C(_x)				PERF_COUNT_HW_CACHE_##_x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define CACHE_OP_UNSUPPORTED		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /* Enough for both software and hardware defined events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define SOFTWARE_EVENT_MASK		0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define PFM_OFFSET_MAGIC_0		2	/* DO NOT START FROM 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define PFM_OFFSET_MAGIC_1		(PFM_OFFSET_MAGIC_0 + 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define PFM_OFFSET_MAGIC_2		(PFM_OFFSET_MAGIC_1 + 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) enum { PFMC0, PFMC1, PFMC2, MAX_COUNTERS };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) u32 PFM_CTL_OVF[3] = { PFM_CTL_mskOVF0, PFM_CTL_mskOVF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		       PFM_CTL_mskOVF2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) u32 PFM_CTL_EN[3] = { PFM_CTL_mskEN0, PFM_CTL_mskEN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		      PFM_CTL_mskEN2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) u32 PFM_CTL_OFFSEL[3] = { PFM_CTL_offSEL0, PFM_CTL_offSEL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 			  PFM_CTL_offSEL2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) u32 PFM_CTL_IE[3] = { PFM_CTL_mskIE0, PFM_CTL_mskIE1, PFM_CTL_mskIE2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) u32 PFM_CTL_KS[3] = { PFM_CTL_mskKS0, PFM_CTL_mskKS1, PFM_CTL_mskKS2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) u32 PFM_CTL_KU[3] = { PFM_CTL_mskKU0, PFM_CTL_mskKU1, PFM_CTL_mskKU2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) u32 PFM_CTL_SEL[3] = { PFM_CTL_mskSEL0, PFM_CTL_mskSEL1, PFM_CTL_mskSEL2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * Perf Events' indices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define NDS32_IDX_CYCLE_COUNTER			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define NDS32_IDX_COUNTER0			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define NDS32_IDX_COUNTER1			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* The events for a given PMU register set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) struct pmu_hw_events {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	 * The events that are active on the PMU for the given index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct perf_event *events[MAX_COUNTERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	 * A 1 bit for an index indicates that the counter is being used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	 * an event. A 0 means that the counter can be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	unsigned long used_mask[BITS_TO_LONGS(MAX_COUNTERS)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	 * Hardware lock to serialize accesses to PMU registers. Needed for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	 * read/modify/write sequences.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	raw_spinlock_t pmu_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) struct nds32_pmu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct pmu pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	cpumask_t active_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	 irqreturn_t (*handle_irq)(int irq_num, void *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	void (*enable)(struct perf_event *event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	void (*disable)(struct perf_event *event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	int (*get_event_idx)(struct pmu_hw_events *hw_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			     struct perf_event *event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	int (*set_event_filter)(struct hw_perf_event *evt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 				struct perf_event_attr *attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	u32 (*read_counter)(struct perf_event *event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	void (*write_counter)(struct perf_event *event, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	void (*start)(struct nds32_pmu *nds32_pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	void (*stop)(struct nds32_pmu *nds32_pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	void (*reset)(void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	int (*request_irq)(struct nds32_pmu *nds32_pmu, irq_handler_t handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	void (*free_irq)(struct nds32_pmu *nds32_pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	int (*map_event)(struct perf_event *event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	int num_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	atomic_t active_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	u64 max_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct platform_device *plat_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct pmu_hw_events *(*get_hw_events)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define to_nds32_pmu(p)			(container_of(p, struct nds32_pmu, pmu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) int nds32_pmu_register(struct nds32_pmu *nds32_pmu, int type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) u64 nds32_pmu_event_update(struct perf_event *event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) int nds32_pmu_event_set_period(struct perf_event *event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  * Common NDS32 SPAv3 event types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  * Note: An implementation may not be able to count all of these events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  * but the encodings are considered to be `reserved' in the case that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  * they are not available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  * SEL_TOTAL_CYCLES will add an offset is due to ZERO is defined as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  * NOT_SUPPORTED EVENT mapping in generic perf code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  * You will need to deal it in the event writing implementation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) enum spav3_counter_0_perf_types {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	SPAV3_0_SEL_BASE = -1 + PFM_OFFSET_MAGIC_0,	/* counting symbol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	SPAV3_0_SEL_TOTAL_CYCLES = 0 + PFM_OFFSET_MAGIC_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	SPAV3_0_SEL_COMPLETED_INSTRUCTION = 1 + PFM_OFFSET_MAGIC_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	SPAV3_0_SEL_LAST	/* counting symbol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) enum spav3_counter_1_perf_types {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	SPAV3_1_SEL_BASE = -1 + PFM_OFFSET_MAGIC_1,	/* counting symbol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	SPAV3_1_SEL_TOTAL_CYCLES = 0 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	SPAV3_1_SEL_COMPLETED_INSTRUCTION = 1 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	SPAV3_1_SEL_CONDITIONAL_BRANCH = 2 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	SPAV3_1_SEL_TAKEN_CONDITIONAL_BRANCH = 3 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	SPAV3_1_SEL_PREFETCH_INSTRUCTION = 4 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	SPAV3_1_SEL_RET_INST = 5 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	SPAV3_1_SEL_JR_INST = 6 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	SPAV3_1_SEL_JAL_JRAL_INST = 7 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	SPAV3_1_SEL_NOP_INST = 8 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	SPAV3_1_SEL_SCW_INST = 9 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	SPAV3_1_SEL_ISB_DSB_INST = 10 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	SPAV3_1_SEL_CCTL_INST = 11 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	SPAV3_1_SEL_TAKEN_INTERRUPTS = 12 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	SPAV3_1_SEL_LOADS_COMPLETED = 13 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	SPAV3_1_SEL_UITLB_ACCESS = 14 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	SPAV3_1_SEL_UDTLB_ACCESS = 15 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	SPAV3_1_SEL_MTLB_ACCESS = 16 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	SPAV3_1_SEL_CODE_CACHE_ACCESS = 17 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	SPAV3_1_SEL_DATA_DEPENDENCY_STALL_CYCLES = 18 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	SPAV3_1_SEL_DATA_CACHE_MISS_STALL_CYCLES = 19 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	SPAV3_1_SEL_DATA_CACHE_ACCESS = 20 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	SPAV3_1_SEL_DATA_CACHE_MISS = 21 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	SPAV3_1_SEL_LOAD_DATA_CACHE_ACCESS = 22 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	SPAV3_1_SEL_STORE_DATA_CACHE_ACCESS = 23 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	SPAV3_1_SEL_ILM_ACCESS = 24 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	SPAV3_1_SEL_LSU_BIU_CYCLES = 25 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	SPAV3_1_SEL_HPTWK_BIU_CYCLES = 26 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	SPAV3_1_SEL_DMA_BIU_CYCLES = 27 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	SPAV3_1_SEL_CODE_CACHE_FILL_BIU_CYCLES = 28 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	SPAV3_1_SEL_LEGAL_UNALIGN_DCACHE_ACCESS = 29 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	SPAV3_1_SEL_PUSH25 = 30 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	SPAV3_1_SEL_SYSCALLS_INST = 31 + PFM_OFFSET_MAGIC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	SPAV3_1_SEL_LAST	/* counting symbol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) enum spav3_counter_2_perf_types {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	SPAV3_2_SEL_BASE = -1 + PFM_OFFSET_MAGIC_2,	/* counting symbol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	SPAV3_2_SEL_TOTAL_CYCLES = 0 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	SPAV3_2_SEL_COMPLETED_INSTRUCTION = 1 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	SPAV3_2_SEL_CONDITIONAL_BRANCH_MISPREDICT = 2 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	SPAV3_2_SEL_TAKEN_CONDITIONAL_BRANCH_MISPREDICT =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	    3 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	SPAV3_2_SEL_PREFETCH_INSTRUCTION_CACHE_HIT = 4 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	SPAV3_1_SEL_RET_MISPREDICT = 5 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	SPAV3_1_SEL_IMMEDIATE_J_INST = 6 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	SPAV3_1_SEL_MULTIPLY_INST = 7 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	SPAV3_1_SEL_16_BIT_INST = 8 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	SPAV3_1_SEL_FAILED_SCW_INST = 9 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	SPAV3_1_SEL_LD_AFTER_ST_CONFLICT_REPLAYS = 10 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	SPAV3_1_SEL_TAKEN_EXCEPTIONS = 12 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	SPAV3_1_SEL_STORES_COMPLETED = 13 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	SPAV3_2_SEL_UITLB_MISS = 14 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	SPAV3_2_SEL_UDTLB_MISS = 15 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	SPAV3_2_SEL_MTLB_MISS = 16 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	SPAV3_2_SEL_CODE_CACHE_MISS = 17 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	SPAV3_1_SEL_EMPTY_INST_QUEUE_STALL_CYCLES = 18 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	SPAV3_1_SEL_DATA_WRITE_BACK = 19 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	SPAV3_2_SEL_DATA_CACHE_MISS = 21 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	SPAV3_2_SEL_LOAD_DATA_CACHE_MISS = 22 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	SPAV3_2_SEL_STORE_DATA_CACHE_MISS = 23 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	SPAV3_1_SEL_DLM_ACCESS = 24 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	SPAV3_1_SEL_LSU_BIU_REQUEST = 25 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	SPAV3_1_SEL_HPTWK_BIU_REQUEST = 26 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	SPAV3_1_SEL_DMA_BIU_REQUEST = 27 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	SPAV3_1_SEL_CODE_CACHE_FILL_BIU_REQUEST = 28 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	SPAV3_1_SEL_EXTERNAL_EVENTS = 29 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	SPAV3_1_SEL_POP25 = 30 + PFM_OFFSET_MAGIC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	SPAV3_2_SEL_LAST	/* counting symbol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Get converted event counter index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static inline int get_converted_event_idx(unsigned long event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if ((event) > SPAV3_0_SEL_BASE && event < SPAV3_0_SEL_LAST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	} else if ((event) > SPAV3_1_SEL_BASE && event < SPAV3_1_SEL_LAST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		idx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	} else if ((event) > SPAV3_2_SEL_BASE && event < SPAV3_2_SEL_LAST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		idx = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		pr_err("GET_CONVERTED_EVENT_IDX PFM counter range error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	return idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Get converted hardware event number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static inline u32 get_converted_evet_hw_num(u32 event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (event > SPAV3_0_SEL_BASE && event < SPAV3_0_SEL_LAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		event -= PFM_OFFSET_MAGIC_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	else if (event > SPAV3_1_SEL_BASE && event < SPAV3_1_SEL_LAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		event -= PFM_OFFSET_MAGIC_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	else if (event > SPAV3_2_SEL_BASE && event < SPAV3_2_SEL_LAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		event -= PFM_OFFSET_MAGIC_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	else if (event != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		pr_err("GET_CONVERTED_EVENT_HW_NUM PFM counter range error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	return event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)  * NDS32 HW events mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  * The hardware events that we support. We do support cache operations but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  * we have harvard caches and no way to combine instruction and data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)  * accesses/misses in hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const unsigned int nds32_pfm_perf_map[PERF_COUNT_HW_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	[PERF_COUNT_HW_CPU_CYCLES] = SPAV3_0_SEL_TOTAL_CYCLES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	[PERF_COUNT_HW_INSTRUCTIONS] = SPAV3_1_SEL_COMPLETED_INSTRUCTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	[PERF_COUNT_HW_CACHE_REFERENCES] = SPAV3_1_SEL_DATA_CACHE_ACCESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	[PERF_COUNT_HW_CACHE_MISSES] = SPAV3_2_SEL_DATA_CACHE_MISS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = HW_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	[PERF_COUNT_HW_BRANCH_MISSES] = HW_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	[PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	[PERF_COUNT_HW_REF_CPU_CYCLES] = HW_OP_UNSUPPORTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const unsigned int nds32_pfm_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	[PERF_COUNT_HW_CACHE_OP_MAX]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	[C(L1D)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		    [C(OP_READ)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 				    [C(RESULT_ACCESS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 				    SPAV3_1_SEL_LOAD_DATA_CACHE_ACCESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 				    [C(RESULT_MISS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 				    SPAV3_2_SEL_LOAD_DATA_CACHE_MISS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 				    },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		    [C(OP_WRITE)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 				     [C(RESULT_ACCESS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 				     SPAV3_1_SEL_STORE_DATA_CACHE_ACCESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 				     [C(RESULT_MISS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 				     SPAV3_2_SEL_STORE_DATA_CACHE_MISS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 				     },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		    [C(OP_PREFETCH)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 					[C(RESULT_ACCESS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 						CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 					[C(RESULT_MISS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 						CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 					},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		    },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	[C(L1I)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		    [C(OP_READ)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 				    [C(RESULT_ACCESS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 				    SPAV3_1_SEL_CODE_CACHE_ACCESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 				    [C(RESULT_MISS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 				    SPAV3_2_SEL_CODE_CACHE_MISS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 				    },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		    [C(OP_WRITE)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 				     [C(RESULT_ACCESS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 				     SPAV3_1_SEL_CODE_CACHE_ACCESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 				     [C(RESULT_MISS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 				     SPAV3_2_SEL_CODE_CACHE_MISS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 				     },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		    [C(OP_PREFETCH)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 					[C(RESULT_ACCESS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 					CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 					[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 					},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		    },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	/* TODO: L2CC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	[C(LL)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		   [C(OP_READ)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 				   [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 				   [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 				   },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		   [C(OP_WRITE)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 				    [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 				    [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 				    },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		   [C(OP_PREFETCH)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 				       [C(RESULT_ACCESS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 				       CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 				       [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 				       },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		   },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	/* NDS32 PMU does not support TLB read/write hit/miss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	 * However, it can count access/miss, which mixed with read and write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	 * Therefore, only READ counter will use it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	 * We do as possible as we can.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	[C(DTLB)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		     [C(OP_READ)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 				     [C(RESULT_ACCESS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 					SPAV3_1_SEL_UDTLB_ACCESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 				     [C(RESULT_MISS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 					SPAV3_2_SEL_UDTLB_MISS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 				     },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		     [C(OP_WRITE)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 				      [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 				      [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 				      },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		     [C(OP_PREFETCH)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 					 [C(RESULT_ACCESS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 					 CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 					 [C(RESULT_MISS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 					 CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 					 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		     },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	[C(ITLB)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		     [C(OP_READ)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 				     [C(RESULT_ACCESS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 					SPAV3_1_SEL_UITLB_ACCESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 				     [C(RESULT_MISS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 					SPAV3_2_SEL_UITLB_MISS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 				     },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		     [C(OP_WRITE)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 				      [C(RESULT_ACCESS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 					CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 				      [C(RESULT_MISS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 					CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 				      },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		     [C(OP_PREFETCH)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 					 [C(RESULT_ACCESS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 						CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 					 [C(RESULT_MISS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 						CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 					 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		     },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	[C(BPU)] = {		/* What is BPU? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		    [C(OP_READ)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 				    [C(RESULT_ACCESS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 					CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 				    [C(RESULT_MISS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 					CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 				    },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		    [C(OP_WRITE)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 				     [C(RESULT_ACCESS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 					CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 				     [C(RESULT_MISS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 					CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 				     },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		    [C(OP_PREFETCH)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 					[C(RESULT_ACCESS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 						CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 					[C(RESULT_MISS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 						CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 					},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		    },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	[C(NODE)] = {		/* What is NODE? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		     [C(OP_READ)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 				     [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 				     [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 				     },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		     [C(OP_WRITE)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 				      [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 				      [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 				      },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		     [C(OP_PREFETCH)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 					 [C(RESULT_ACCESS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 						CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 					 [C(RESULT_MISS)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 						CACHE_OP_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 					 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		     },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int nds32_pmu_map_event(struct perf_event *event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 			const unsigned int (*event_map)[PERF_COUNT_HW_MAX],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 			const unsigned int (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 			[PERF_COUNT_HW_CACHE_OP_MAX]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 			[PERF_COUNT_HW_CACHE_RESULT_MAX], u32 raw_event_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #endif /* __ASM_PMU_H */