Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) // Copyright (C) 2005-2017 Andes Technology Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #ifndef _ASMNDS32_PGTABLE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #define _ASMNDS32_PGTABLE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <asm-generic/pgtable-nopmd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <asm/memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <asm/nds32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/fixmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <nds32_intrinsic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #ifdef CONFIG_ANDES_PAGE_SIZE_4KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define PGDIR_SHIFT      22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define PTRS_PER_PGD     1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define PTRS_PER_PTE     1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #ifdef CONFIG_ANDES_PAGE_SIZE_8KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define PGDIR_SHIFT      24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define PTRS_PER_PGD     256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define PTRS_PER_PTE     2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) extern void __pte_error(const char *file, int line, unsigned long val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) extern void __pgd_error(const char *file, int line, unsigned long val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define pte_ERROR(pte)		__pte_error(__FILE__, __LINE__, pte_val(pte))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define pgd_ERROR(pgd)		__pgd_error(__FILE__, __LINE__, pgd_val(pgd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #endif /* !__ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define PMD_SIZE		(1UL << PMD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define PMD_MASK		(~(PMD_SIZE-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define PGDIR_SIZE		(1UL << PGDIR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define PGDIR_MASK		(~(PGDIR_SIZE-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * This is the lowest virtual address we can permit any user space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * mapping to be mapped at.  This is particularly important for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * non-high vector CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define FIRST_USER_ADDRESS	0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #ifdef CONFIG_HIGHMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define CONSISTENT_BASE		((PKMAP_BASE) - (SZ_2M))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define CONSISTENT_END		(PKMAP_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define CONSISTENT_BASE		(FIXADDR_START - SZ_2M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define CONSISTENT_END		(FIXADDR_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define CONSISTENT_OFFSET(x)	(((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #ifdef CONFIG_HIGHMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #include <asm/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define VMALLOC_RESERVE 	SZ_128M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define VMALLOC_END		(CONSISTENT_BASE - PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define VMALLOC_START		((VMALLOC_END) - VMALLOC_RESERVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define VMALLOC_VMADDR(x)	((unsigned long)(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define MAXMEM			__pa(VMALLOC_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define MAXMEM_PFN		PFN_DOWN(MAXMEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define FIRST_USER_PGD_NR	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define USER_PTRS_PER_PGD	((TASK_SIZE/PGDIR_SIZE) + FIRST_USER_PGD_NR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /* L2 PTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define _PAGE_V			(1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define _PAGE_M_XKRW            (0UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define _PAGE_M_UR_KR		(1UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define _PAGE_M_UR_KRW		(2UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define _PAGE_M_URW_KRW		(3UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define _PAGE_M_KR		(5UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define _PAGE_M_KRW		(7UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define _PAGE_D			(1UL << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define _PAGE_E			(1UL << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define _PAGE_A			(1UL << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define _PAGE_G			(1UL << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define _PAGE_C_DEV		(0UL << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define _PAGE_C_DEV_WB		(1UL << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define _PAGE_C_MEM		(2UL << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define _PAGE_C_MEM_SHRD_WB	(4UL << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define _PAGE_C_MEM_SHRD_WT	(5UL << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define _PAGE_C_MEM_WB		(6UL << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define _PAGE_C_MEM_WT		(7UL << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define _PAGE_L			(1UL << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define _HAVE_PAGE_L		(_PAGE_L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define _PAGE_FILE		(1UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define _PAGE_YOUNG		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define _PAGE_M_MASK		_PAGE_M_KRW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define _PAGE_C_MASK		_PAGE_C_MEM_WT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define _PAGE_CACHE_SHRD	_PAGE_C_MEM_SHRD_WT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define _PAGE_CACHE_SHRD	_PAGE_C_MEM_SHRD_WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define _PAGE_CACHE_SHRD	_PAGE_C_MEM_WT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define _PAGE_CACHE_SHRD	_PAGE_C_MEM_WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define _PAGE_CACHE		_PAGE_C_MEM_WT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define _PAGE_CACHE		_PAGE_C_MEM_WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define _PAGE_IOREMAP \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	(_PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_G | _PAGE_C_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  * + Level 1 descriptor (PMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PMD_TYPE_TABLE		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define _PAGE_USER_TABLE     PMD_TYPE_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define _PAGE_KERNEL_TABLE   PMD_TYPE_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PAGE_EXEC	__pgprot(_PAGE_V | _PAGE_M_XKRW | _PAGE_E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PAGE_NONE	__pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PAGE_READ	__pgprot(_PAGE_V | _PAGE_M_UR_KR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PAGE_RDWR	__pgprot(_PAGE_V | _PAGE_M_URW_KRW | _PAGE_D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PAGE_COPY	__pgprot(_PAGE_V | _PAGE_M_UR_KR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PAGE_UXKRWX_V1	__pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PAGE_UXKRWX_V2	__pgprot(_PAGE_V | _PAGE_M_XKRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PAGE_URXKRWX_V2	__pgprot(_PAGE_V | _PAGE_M_UR_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PAGE_CACHE_L1	__pgprot(_HAVE_PAGE_L | _PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PAGE_MEMORY	__pgprot(_HAVE_PAGE_L | _PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PAGE_KERNEL	__pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PAGE_SHARED	__pgprot(_PAGE_V | _PAGE_M_URW_KRW | _PAGE_D | _PAGE_CACHE_SHRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PAGE_DEVICE    __pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_G | _PAGE_C_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*         xwr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define __P000  (PAGE_NONE | _PAGE_CACHE_SHRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define __P001  (PAGE_READ | _PAGE_CACHE_SHRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define __P010  (PAGE_COPY | _PAGE_CACHE_SHRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define __P011  (PAGE_COPY | _PAGE_CACHE_SHRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define __P100  (PAGE_EXEC | _PAGE_CACHE_SHRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define __P101  (PAGE_READ | _PAGE_E | _PAGE_CACHE_SHRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define __P110  (PAGE_COPY | _PAGE_E | _PAGE_CACHE_SHRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define __P111  (PAGE_COPY | _PAGE_E | _PAGE_CACHE_SHRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define __S000  (PAGE_NONE | _PAGE_CACHE_SHRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define __S001  (PAGE_READ | _PAGE_CACHE_SHRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define __S010  (PAGE_RDWR | _PAGE_CACHE_SHRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define __S011  (PAGE_RDWR | _PAGE_CACHE_SHRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define __S100  (PAGE_EXEC | _PAGE_CACHE_SHRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define __S101  (PAGE_READ | _PAGE_E | _PAGE_CACHE_SHRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define __S110  (PAGE_RDWR | _PAGE_E | _PAGE_CACHE_SHRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define __S111  (PAGE_RDWR | _PAGE_E | _PAGE_CACHE_SHRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)  * ZERO_PAGE is a global shared page that is always zero: used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)  * for zero-mapped memory areas etc..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) extern struct page *empty_zero_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) extern void paging_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ZERO_PAGE(vaddr)	(empty_zero_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define pte_pfn(pte)		(pte_val(pte) >> PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define pfn_pte(pfn,prot)	(__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define pte_none(pte)	        !(pte_val(pte))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define pte_clear(mm,addr,ptep)	set_pte_at((mm),(addr),(ptep), __pte(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define pte_page(pte)		(pfn_to_page(pte_pfn(pte)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static unsigned long pmd_page_vaddr(pmd_t pmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  * Set a level 1 translation table entry, and clean it out of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  * any caches such that the MMUs can load it correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static inline void set_pmd(pmd_t * pmdp, pmd_t pmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	*pmdp = pmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #if !defined(CONFIG_CPU_DCACHE_DISABLE) && !defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (pmdp):"memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	__nds32__msync_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	__nds32__dsb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  * Set a PTE and flush it out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static inline void set_pte(pte_t * ptep, pte_t pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	*ptep = pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #if !defined(CONFIG_CPU_DCACHE_DISABLE) && !defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (ptep):"memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	__nds32__msync_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	__nds32__dsb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  * The following only work if pte_present() is true.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)  * Undefined behaviour if not..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)  * pte_write: 	     this page is writeable for user mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)  * pte_read:         this page is readable for user mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)  * pte_kernel_write: this page is writeable for kernel mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)  * We don't have pte_kernel_read because kernel always can read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)  * */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define pte_present(pte)        (pte_val(pte) & _PAGE_V)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define pte_write(pte)          ((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_URW_KRW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define pte_read(pte)		(((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_UR_KR) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 				((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_UR_KRW) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 				((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_URW_KRW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define pte_kernel_write(pte)   (((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_URW_KRW) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 				((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_UR_KRW) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 				((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_KRW) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 				(((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_XKRW) && pte_exec(pte)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define pte_exec(pte)		(pte_val(pte) & _PAGE_E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define pte_dirty(pte)		(pte_val(pte) & _PAGE_D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define pte_young(pte)		(pte_val(pte) & _PAGE_YOUNG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)  * The following only works if pte_present() is not true.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define pte_file(pte)		(pte_val(pte) & _PAGE_FILE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define pte_to_pgoff(x)		(pte_val(x) >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define pgoff_to_pte(x)		__pte(((x) << 2) | _PAGE_FILE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define PTE_FILE_MAX_BITS	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define PTE_BIT_FUNC(fn,op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static inline pte_t pte_wrprotect(pte_t pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	pte_val(pte) = pte_val(pte) & ~_PAGE_M_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	pte_val(pte) = pte_val(pte) | _PAGE_M_UR_KR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	return pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static inline pte_t pte_mkwrite(pte_t pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	pte_val(pte) = pte_val(pte) & ~_PAGE_M_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	pte_val(pte) = pte_val(pte) | _PAGE_M_URW_KRW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	return pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PTE_BIT_FUNC(exprotect, &=~_PAGE_E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PTE_BIT_FUNC(mkexec, |=_PAGE_E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PTE_BIT_FUNC(mkclean, &=~_PAGE_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PTE_BIT_FUNC(mkdirty, |=_PAGE_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PTE_BIT_FUNC(mkold, &=~_PAGE_YOUNG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PTE_BIT_FUNC(mkyoung, |=_PAGE_YOUNG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)  * Mark the prot value as uncacheable and unbufferable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define pgprot_noncached(prot)	   __pgprot((pgprot_val(prot)&~_PAGE_C_MASK) | _PAGE_C_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define pgprot_writecombine(prot)  __pgprot((pgprot_val(prot)&~_PAGE_C_MASK) | _PAGE_C_DEV_WB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define pmd_none(pmd)         (pmd_val(pmd)&0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define pmd_present(pmd)      (!pmd_none(pmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define	pmd_bad(pmd)	      pmd_none(pmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define copy_pmd(pmdpd,pmdps)	set_pmd((pmdpd), *(pmdps))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define pmd_clear(pmdp)		set_pmd((pmdp), __pmd(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static inline pmd_t __mk_pmd(pte_t * ptep, unsigned long prot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	unsigned long ptr = (unsigned long)ptep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	pmd_t pmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	 * The pmd must be loaded with the physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	 * address of the PTE table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	pmd_val(pmd) = __virt_to_phys(ptr) | prot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	return pmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define pmd_page(pmd)        virt_to_page(__va(pmd_val(pmd)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)  * Permanent address of a page. We never have highmem, so this is trivial.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define pages_to_mb(x)       ((x) >> (20 - PAGE_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)  * Conversion functions: convert a page and protection to a page entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)  * and a page entry and page directory to the page they refer to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define mk_pte(page,prot)	pfn_pte(page_to_pfn(page),prot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)  * The "pgd_xxx()" functions here are trivial for a folded two-level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)  * setup: the pgd is never bad, and a pmd always exists (as it's folded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)  * into the pgd entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define pgd_none(pgd)		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define pgd_bad(pgd)		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define pgd_present(pgd)  	(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define pgd_clear(pgdp)		do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define page_pte_prot(page,prot)     	mk_pte(page, prot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define page_pte(page)		        mk_pte(page, __pgprot(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)  *     L1PTE = $mr1 + ((virt >> PMD_SHIFT) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)  *     L2PTE = (((virt >> PAGE_SHIFT) & (PTRS_PER_PTE -1 )) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)  *     PPN = (phys & 0xfffff000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	const unsigned long mask = 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	return pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* Encode and decode a swap entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)  * We support up to 32GB of swap on 4k machines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define __swp_type(x)	 	     (((x).val >> 2) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define __swp_offset(x)	   	     ((x).val >> 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define __swp_entry(type,offset)     ((swp_entry_t) { ((type) << 2) | ((offset) << 9) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define __pte_to_swp_entry(pte)	     ((swp_entry_t) { pte_val(pte) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define __swp_entry_to_pte(swp)	     ((pte_t) { (swp).val })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define kern_addr_valid(addr)	(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)  * We provide our own arch_get_unmapped_area to cope with VIPT caches.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define HAVE_ARCH_UNMAPPED_AREA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)  * remap a physical address `phys' of size `size' with page protection `prot'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)  * into virtual address `from'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #endif /* !__ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #endif /* _ASMNDS32_PGTABLE_H */