^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (C) 2005-2017 Andes Technology Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #ifndef _ASM_NDS32_NDS32_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define _ASM_NDS32_NDS32_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <asm/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm/cachectl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/barrier.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <nds32_intrinsic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define FP_OFFSET (-3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define FP_OFFSET (-2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LP_OFFSET (-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) extern void __init early_trap_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static inline void GIE_ENABLE(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) __nds32__gie_en();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static inline void GIE_DISABLE(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) __nds32__gie_dis();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static inline unsigned long CACHE_SET(unsigned char cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (cache == ICACHE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return 64 << ((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskISET) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ICM_CFG_offISET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return 64 << ((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDSET) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) DCM_CFG_offDSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static inline unsigned long CACHE_WAY(unsigned char cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (cache == ICACHE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return 1 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskIWAY) >> ICM_CFG_offIWAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return 1 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDWAY) >> DCM_CFG_offDWAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static inline unsigned long CACHE_LINE_SIZE(unsigned char cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (cache == ICACHE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return 8 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) (((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskISZ) >> ICM_CFG_offISZ) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return 8 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) (((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDSZ) >> DCM_CFG_offDSZ) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IVB_BASE PHYS_OFFSET /* in user space for intr/exc/trap/break table base, 64KB aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * We defined at the start of the physical memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* dispatched sub-entry exception handler numbering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RD_PROT 0 /* read protrection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define WRT_PROT 1 /* write protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define NOEXEC 2 /* non executable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PAGE_MODIFY 3 /* page modified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ACC_BIT 4 /* access bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RESVED_PTE 5 /* reserved PTE attribute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* reserved 6 ~ 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #endif /* _ASM_NDS32_NDS32_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags