^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (C) 2005-2017 Andes Technology Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #ifndef __ASM_NDS32_IO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define __ASM_NDS32_IO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __raw_writeb __raw_writeb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) asm volatile("sbi %0, [%1]" : : "r" (val), "r" (addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define __raw_writew __raw_writew
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static inline void __raw_writew(u16 val, volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) asm volatile("shi %0, [%1]" : : "r" (val), "r" (addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define __raw_writel __raw_writel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static inline void __raw_writel(u32 val, volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) asm volatile("swi %0, [%1]" : : "r" (val), "r" (addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define __raw_readb __raw_readb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static inline u8 __raw_readb(const volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) asm volatile("lbi %0, [%1]" : "=r" (val) : "r" (addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define __raw_readw __raw_readw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static inline u16 __raw_readw(const volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) asm volatile("lhi %0, [%1]" : "=r" (val) : "r" (addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define __raw_readl __raw_readl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static inline u32 __raw_readl(const volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) asm volatile("lwi %0, [%1]" : "=r" (val) : "r" (addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define __iormb() rmb()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define __iowmb() wmb()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * {read,write}{b,w,l,q}_relaxed() are like the regular version, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * are not guaranteed to provide ordering against spinlocks or memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * accesses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define readb_relaxed(c) ({ u8 __v = __raw_readb(c); __v; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16)__raw_readw(c)); __v; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32)__raw_readl(c)); __v; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * {read,write}{b,w,l,q}() access little endian memory and return result in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * native endianness.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define writeb(v,c) ({ __iowmb(); writeb_relaxed((v),(c)); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #include <asm-generic/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #endif /* __ASM_NDS32_IO_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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