Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) // Copyright (C) 2005-2017 Andes Technology Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #ifndef __NDS32_DELAY_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #define __NDS32_DELAY_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <asm/param.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /* There is no clocksource cycle counter in the CPU. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) static inline void __delay(unsigned long loops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	__asm__ __volatile__(".align 2\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 			     "1:\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 			     "\taddi\t%0, %0, -1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 			     "\tbgtz\t%0, 1b\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 			     :"=r"(loops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 			     :"0"(loops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static inline void __udelay(unsigned long usecs, unsigned long lpj)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	usecs *= (unsigned long)(((0x8000000000000000ULL / (500000 / HZ)) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 				  0x80000000ULL) >> 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	usecs = (unsigned long)(((unsigned long long)usecs * lpj) >> 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	__delay(usecs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define udelay(usecs) __udelay((usecs), loops_per_jiffy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* make sure "usecs *= ..." in udelay do not overflow. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #if HZ >= 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MAX_UDELAY_MS	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #elif HZ <= 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MAX_UDELAY_MS	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MAX_UDELAY_MS	(1000 / HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif