^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (C) 2005-2017 Andes Technology Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #ifndef __NDS32_BITFIELD_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define __NDS32_BITFIELD_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * cr0: CPU_VER (CPU Version Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define CPU_VER_offCFGID 0 /* Minor configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CPU_VER_offREV 16 /* Revision of the CPU version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CPU_VER_offCPUID 24 /* Major CPU versions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CPU_VER_mskCFGID ( 0xFFFF << CPU_VER_offCFGID )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CPU_VER_mskREV ( 0xFF << CPU_VER_offREV )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CPU_VER_mskCPUID ( 0xFF << CPU_VER_offCPUID )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * cr1: ICM_CFG (Instruction Cache/Memory Configuration Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ICM_CFG_offISET 0 /* I-cache sets (# of cache lines) per way */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ICM_CFG_offIWAY 3 /* I-cache ways */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ICM_CFG_offISZ 6 /* I-cache line size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ICM_CFG_offILCK 9 /* I-cache locking support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ICM_CFG_offILMB 10 /* On-chip ILM banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ICM_CFG_offBSAV 13 /* ILM base register alignment version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* bit 15:31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ICM_CFG_mskISET ( 0x7 << ICM_CFG_offISET )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ICM_CFG_mskIWAY ( 0x7 << ICM_CFG_offIWAY )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ICM_CFG_mskISZ ( 0x7 << ICM_CFG_offISZ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ICM_CFG_mskILCK ( 0x1 << ICM_CFG_offILCK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ICM_CFG_mskILMB ( 0x7 << ICM_CFG_offILMB )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ICM_CFG_mskBSAV ( 0x3 << ICM_CFG_offBSAV )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * cr2: DCM_CFG (Data Cache/Memory Configuration Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DCM_CFG_offDSET 0 /* D-cache sets (# of cache lines) per way */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DCM_CFG_offDWAY 3 /* D-cache ways */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DCM_CFG_offDSZ 6 /* D-cache line size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DCM_CFG_offDLCK 9 /* D-cache locking support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DCM_CFG_offDLMB 10 /* On-chip DLM banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DCM_CFG_offBSAV 13 /* DLM base register alignment version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* bit 15:31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DCM_CFG_mskDSET ( 0x7 << DCM_CFG_offDSET )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DCM_CFG_mskDWAY ( 0x7 << DCM_CFG_offDWAY )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DCM_CFG_mskDSZ ( 0x7 << DCM_CFG_offDSZ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DCM_CFG_mskDLCK ( 0x1 << DCM_CFG_offDLCK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DCM_CFG_mskDLMB ( 0x7 << DCM_CFG_offDLMB )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DCM_CFG_mskBSAV ( 0x3 << DCM_CFG_offBSAV )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * cr3: MMU_CFG (MMU Configuration Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MMU_CFG_offMMPS 0 /* Memory management protection scheme */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MMU_CFG_offMMPV 2 /* Memory management protection version number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MMU_CFG_offFATB 7 /* Fully-associative or non-fully-associative TLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MMU_CFG_offTBW 8 /* TLB ways(non-associative) TBS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MMU_CFG_offTBS 11 /* TLB sets per way(non-associative) TBS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* bit 14:14 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MMU_CFG_offEP8MIN4 15 /* 8KB page supported while minimum page is 4KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MMU_CFG_offfEPSZ 16 /* Extra page size supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MMU_CFG_offTLBLCK 24 /* TLB locking support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MMU_CFG_offHPTWK 25 /* Hardware Page Table Walker implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MMU_CFG_offDE 26 /* Default endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MMU_CFG_offNTPT 27 /* Partitions for non-translated attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MMU_CFG_offIVTB 28 /* Invisible TLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MMU_CFG_offVLPT 29 /* VLPT for fast TLB fill handling implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MMU_CFG_offNTME 30 /* Non-translated VA to PA mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* bit 31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MMU_CFG_mskMMPS ( 0x3 << MMU_CFG_offMMPS )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MMU_CFG_mskMMPV ( 0x1F << MMU_CFG_offMMPV )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MMU_CFG_mskFATB ( 0x1 << MMU_CFG_offFATB )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MMU_CFG_mskTBW ( 0x7 << MMU_CFG_offTBW )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MMU_CFG_mskTBS ( 0x7 << MMU_CFG_offTBS )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MMU_CFG_mskEP8MIN4 ( 0x1 << MMU_CFG_offEP8MIN4 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MMU_CFG_mskfEPSZ ( 0xFF << MMU_CFG_offfEPSZ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MMU_CFG_mskTLBLCK ( 0x1 << MMU_CFG_offTLBLCK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MMU_CFG_mskHPTWK ( 0x1 << MMU_CFG_offHPTWK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MMU_CFG_mskDE ( 0x1 << MMU_CFG_offDE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MMU_CFG_mskNTPT ( 0x1 << MMU_CFG_offNTPT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MMU_CFG_mskIVTB ( 0x1 << MMU_CFG_offIVTB )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MMU_CFG_mskVLPT ( 0x1 << MMU_CFG_offVLPT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MMU_CFG_mskNTME ( 0x1 << MMU_CFG_offNTME )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * cr4: MSC_CFG (Misc Configuration Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MSC_CFG_offEDM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MSC_CFG_offLMDMA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MSC_CFG_offPFM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MSC_CFG_offHSMP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MSC_CFG_offTRACE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MSC_CFG_offDIV 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MSC_CFG_offMAC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MSC_CFG_offAUDIO 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MSC_CFG_offL2C 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MSC_CFG_offRDREG 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MSC_CFG_offADR24 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MSC_CFG_offINTLC 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MSC_CFG_offBASEV 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MSC_CFG_offNOD 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* bit 13:31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MSC_CFG_mskEDM ( 0x1 << MSC_CFG_offEDM )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MSC_CFG_mskLMDMA ( 0x1 << MSC_CFG_offLMDMA )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MSC_CFG_mskPFM ( 0x1 << MSC_CFG_offPFM )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MSC_CFG_mskHSMP ( 0x1 << MSC_CFG_offHSMP )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MSC_CFG_mskTRACE ( 0x1 << MSC_CFG_offTRACE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MSC_CFG_mskDIV ( 0x1 << MSC_CFG_offDIV )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MSC_CFG_mskMAC ( 0x1 << MSC_CFG_offMAC )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MSC_CFG_mskAUDIO ( 0x3 << MSC_CFG_offAUDIO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MSC_CFG_mskL2C ( 0x1 << MSC_CFG_offL2C )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MSC_CFG_mskRDREG ( 0x1 << MSC_CFG_offRDREG )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MSC_CFG_mskADR24 ( 0x1 << MSC_CFG_offADR24 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MSC_CFG_mskINTLC ( 0x1 << MSC_CFG_offINTLC )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MSC_CFG_mskBASEV ( 0x7 << MSC_CFG_offBASEV )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MSC_CFG_mskNOD ( 0x1 << MSC_CFG_offNOD )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * cr5: CORE_CFG (Core Identification Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CORE_ID_offCOREID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* bit 4:31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CORE_ID_mskCOREID ( 0xF << CORE_ID_offCOREID )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * cr6: FUCOP_EXIST (FPU and Coprocessor Existence Configuration Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define FUCOP_EXIST_offCP0EX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define FUCOP_EXIST_offCP1EX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define FUCOP_EXIST_offCP2EX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define FUCOP_EXIST_offCP3EX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define FUCOP_EXIST_offCP0ISFPU 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define FUCOP_EXIST_mskCP0EX ( 0x1 << FUCOP_EXIST_offCP0EX )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define FUCOP_EXIST_mskCP1EX ( 0x1 << FUCOP_EXIST_offCP1EX )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define FUCOP_EXIST_mskCP2EX ( 0x1 << FUCOP_EXIST_offCP2EX )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define FUCOP_EXIST_mskCP3EX ( 0x1 << FUCOP_EXIST_offCP3EX )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define FUCOP_EXIST_mskCP0ISFPU ( 0x1 << FUCOP_EXIST_offCP0ISFPU )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * ir0: PSW (Processor Status Word Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * ir1: IPSW (Interruption PSW Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * ir2: P_IPSW (Previous IPSW Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PSW_offGIE 0 /* Global Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PSW_offINTL 1 /* Interruption Stack Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PSW_offPOM 3 /* Processor Operation Mode, User/Superuser */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PSW_offBE 5 /* Endianness for data memory access, 1:MSB, 0:LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PSW_offIT 6 /* Enable instruction address translation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PSW_offDT 7 /* Enable data address translation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PSW_offIME 8 /* Instruction Machine Error flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PSW_offDME 9 /* Data Machine Error flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PSW_offDEX 10 /* Debug Exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PSW_offHSS 11 /* Hardware Single Stepping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PSW_offDRBE 12 /* Device Register Endian Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PSW_offAEN 13 /* Audio ISA special feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PSW_offWBNA 14 /* Write Back Non-Allocate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PSW_offIFCON 15 /* IFC On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PSW_offCPL 16 /* Current Priority Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* bit 19:31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define PSW_mskGIE ( 0x1 << PSW_offGIE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PSW_mskINTL ( 0x3 << PSW_offINTL )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PSW_mskPOM ( 0x3 << PSW_offPOM )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PSW_mskBE ( 0x1 << PSW_offBE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PSW_mskIT ( 0x1 << PSW_offIT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PSW_mskDT ( 0x1 << PSW_offDT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PSW_mskIME ( 0x1 << PSW_offIME )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PSW_mskDME ( 0x1 << PSW_offDME )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PSW_mskDEX ( 0x1 << PSW_offDEX )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PSW_mskHSS ( 0x1 << PSW_offHSS )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define PSW_mskDRBE ( 0x1 << PSW_offDRBE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define PSW_mskAEN ( 0x1 << PSW_offAEN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define PSW_mskWBNA ( 0x1 << PSW_offWBNA )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define PSW_mskIFCON ( 0x1 << PSW_offIFCON )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define PSW_mskCPL ( 0x7 << PSW_offCPL )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PSW_SYSTEM ( 1 << PSW_offPOM )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PSW_INTL_1 ( 1 << PSW_offINTL )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PSW_CPL_NO ( 0 << PSW_offCPL )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PSW_CPL_ANY ( 7 << PSW_offCPL )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PSW_clr (PSW_mskGIE|PSW_mskINTL|PSW_mskPOM|PSW_mskIT|PSW_mskDT|PSW_mskIME|PSW_mskWBNA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #ifdef __NDS32_EB__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #ifdef CONFIG_WBNA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define PSW_init (PSW_mskWBNA|(1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT|PSW_mskBE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PSW_init ((1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT|PSW_mskBE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #ifdef CONFIG_WBNA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define PSW_init (PSW_mskWBNA|(1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define PSW_init ((1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * ir3: IVB (Interruption Vector Base Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* bit 0:12 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IVB_offNIVIC 1 /* Number of input for IVIC Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define IVB_offIVIC_VER 11 /* IVIC Version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IVB_offEVIC 13 /* External Vector Interrupt Controller mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define IVB_offESZ 14 /* Size of each vector entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define IVB_offIVBASE 16 /* BasePA of interrupt vector table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IVB_mskNIVIC ( 0x7 << IVB_offNIVIC )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define IVB_mskIVIC_VER ( 0x3 << IVB_offIVIC_VER )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IVB_mskEVIC ( 0x1 << IVB_offEVIC )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define IVB_mskESZ ( 0x3 << IVB_offESZ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define IVB_mskIVBASE ( 0xFFFF << IVB_offIVBASE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define IVB_valESZ4 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define IVB_valESZ16 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IVB_valESZ64 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IVB_valESZ256 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * ir4: EVA (Exception Virtual Address Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * ir5: P_EVA (Previous EVA Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* This register contains the VA that causes the exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * ir6: ITYPE (Interruption Type Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * ir7: P_ITYPE (Previous ITYPE Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define ITYPE_offETYPE 0 /* Exception Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define ITYPE_offINST 4 /* Exception caused by insn fetch or data access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* bit 5:15 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define ITYPE_offVECTOR 5 /* Vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define ITYPE_offSWID 16 /* SWID of debugging exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* bit 31:31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define ITYPE_mskETYPE ( 0xF << ITYPE_offETYPE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define ITYPE_mskINST ( 0x1 << ITYPE_offINST )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define ITYPE_mskVECTOR ( 0x7F << ITYPE_offVECTOR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define ITYPE_mskSWID ( 0x7FFF << ITYPE_offSWID )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Additional definitions for ITYPE register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define ITYPE_offSTYPE 16 /* Arithmetic Sub Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define ITYPE_offCPID 20 /* Co-Processor ID which generate the exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define ITYPE_mskSTYPE ( 0xF << ITYPE_offSTYPE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define ITYPE_mskCPID ( 0x3 << ITYPE_offCPID )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Additional definitions of ITYPE register for FPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define FPU_DISABLE_EXCEPTION (0x1 << ITYPE_offSTYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define FPU_EXCEPTION (0x2 << ITYPE_offSTYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define FPU_CPID 0 /* FPU Co-Processor ID is 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define NDS32_VECTOR_mskNONEXCEPTION 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define NDS32_VECTOR_offEXCEPTION 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define NDS32_VECTOR_offINTERRUPT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Interrupt vector entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define ENTRY_RESET_NMI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define ENTRY_TLB_FILL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define ENTRY_PTE_NOT_PRESENT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define ENTRY_TLB_MISC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define ENTRY_TLB_VLPT_MISS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define ENTRY_MACHINE_ERROR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define ENTRY_DEBUG_RELATED 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define ENTRY_GENERAL_EXCPETION 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define ENTRY_SYSCALL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* PTE not present exception definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define ETYPE_NON_LEAF_PTE_NOT_PRESENT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define ETYPE_LEAF_PTE_NOT_PRESENT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* General exception ETYPE definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define ETYPE_ALIGNMENT_CHECK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define ETYPE_RESERVED_INSTRUCTION 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define ETYPE_TRAP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define ETYPE_ARITHMETIC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define ETYPE_PRECISE_BUS_ERROR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define ETYPE_IMPRECISE_BUS_ERROR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define ETYPE_COPROCESSOR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define ETYPE_RESERVED_VALUE 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define ETYPE_NONEXISTENT_MEM_ADDRESS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define ETYPE_MPZIU_CONTROL 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define ETYPE_NEXT_PRECISE_STACK_OFL 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Kerenl reserves software ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SWID_RAISE_INTERRUPT_LEVEL 0x1a /* SWID_RAISE_INTERRUPT_LEVEL is used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * raise interrupt level for debug exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * ir8: MERR (Machine Error Log Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* bit 0:30 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define MERR_offBUSERR 31 /* Bus error caused by a load insn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define MERR_mskBUSERR ( 0x1 << MERR_offBUSERR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * ir9: IPC (Interruption Program Counter Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * ir10: P_IPC (Previous IPC Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * ir11: OIPC (Overflow Interruption Program Counter Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* This is the shadow stack register of the Program Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * ir12: P_P0 (Previous P0 Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * ir13: P_P1 (Previous P1 Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* These are shadow registers of $p0 and $p1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * ir14: INT_MASK (Interruption Masking Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define INT_MASK_offH0IM 0 /* Hardware Interrupt 0 Mask bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define INT_MASK_offH1IM 1 /* Hardware Interrupt 1 Mask bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define INT_MASK_offH2IM 2 /* Hardware Interrupt 2 Mask bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define INT_MASK_offH3IM 3 /* Hardware Interrupt 3 Mask bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define INT_MASK_offH4IM 4 /* Hardware Interrupt 4 Mask bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define INT_MASK_offH5IM 5 /* Hardware Interrupt 5 Mask bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* bit 6:15 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define INT_MASK_offSIM 16 /* Software Interrupt Mask bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* bit 17:29 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define INT_MASK_offIDIVZE 30 /* Enable detection for Divide-By-Zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define INT_MASK_offDSSIM 31 /* Default Single Stepping Interruption Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define INT_MASK_mskH0IM ( 0x1 << INT_MASK_offH0IM )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define INT_MASK_mskH1IM ( 0x1 << INT_MASK_offH1IM )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define INT_MASK_mskH2IM ( 0x1 << INT_MASK_offH2IM )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define INT_MASK_mskH3IM ( 0x1 << INT_MASK_offH3IM )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define INT_MASK_mskH4IM ( 0x1 << INT_MASK_offH4IM )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define INT_MASK_mskH5IM ( 0x1 << INT_MASK_offH5IM )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define INT_MASK_mskSIM ( 0x1 << INT_MASK_offSIM )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define INT_MASK_mskIDIVZE ( 0x1 << INT_MASK_offIDIVZE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define INT_MASK_mskDSSIM ( 0x1 << INT_MASK_offDSSIM )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define INT_MASK_INITAIAL_VAL (INT_MASK_mskDSSIM|INT_MASK_mskIDIVZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * ir15: INT_PEND (Interrupt Pending Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define INT_PEND_offH0I 0 /* Hardware Interrupt 0 pending bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define INT_PEND_offH1I 1 /* Hardware Interrupt 1 pending bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define INT_PEND_offH2I 2 /* Hardware Interrupt 2 pending bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define INT_PEND_offH3I 3 /* Hardware Interrupt 3 pending bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define INT_PEND_offH4I 4 /* Hardware Interrupt 4 pending bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define INT_PEND_offH5I 5 /* Hardware Interrupt 5 pending bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define INT_PEND_offCIPL 0 /* Current Interrupt Priority Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* bit 6:15 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define INT_PEND_offSWI 16 /* Software Interrupt pending bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* bit 17:31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define INT_PEND_mskH0I ( 0x1 << INT_PEND_offH0I )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define INT_PEND_mskH1I ( 0x1 << INT_PEND_offH1I )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define INT_PEND_mskH2I ( 0x1 << INT_PEND_offH2I )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define INT_PEND_mskH3I ( 0x1 << INT_PEND_offH3I )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define INT_PEND_mskH4I ( 0x1 << INT_PEND_offH4I )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define INT_PEND_mskH5I ( 0x1 << INT_PEND_offH5I )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define INT_PEND_mskCIPL ( 0x1 << INT_PEND_offCIPL )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define INT_PEND_mskSWI ( 0x1 << INT_PEND_offSWI )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * mr0: MMU_CTL (MMU Control Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define MMU_CTL_offD 0 /* Default minimum page size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define MMU_CTL_offNTC0 1 /* Non-Translated Cachebility of partition 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define MMU_CTL_offNTC1 3 /* Non-Translated Cachebility of partition 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define MMU_CTL_offNTC2 5 /* Non-Translated Cachebility of partition 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define MMU_CTL_offNTC3 7 /* Non-Translated Cachebility of partition 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define MMU_CTL_offTBALCK 9 /* TLB all-lock resolution scheme */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define MMU_CTL_offMPZIU 10 /* Multiple Page Size In Use bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define MMU_CTL_offNTM0 11 /* Non-Translated VA to PA of partition 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define MMU_CTL_offNTM1 13 /* Non-Translated VA to PA of partition 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define MMU_CTL_offNTM2 15 /* Non-Translated VA to PA of partition 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define MMU_CTL_offNTM3 17 /* Non-Translated VA to PA of partition 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define MMU_CTL_offUNA 23 /* Unaligned access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* bit 24:31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define MMU_CTL_mskD ( 0x1 << MMU_CTL_offD )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define MMU_CTL_mskNTC0 ( 0x3 << MMU_CTL_offNTC0 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define MMU_CTL_mskNTC1 ( 0x3 << MMU_CTL_offNTC1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define MMU_CTL_mskNTC2 ( 0x3 << MMU_CTL_offNTC2 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define MMU_CTL_mskNTC3 ( 0x3 << MMU_CTL_offNTC3 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define MMU_CTL_mskTBALCK ( 0x1 << MMU_CTL_offTBALCK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define MMU_CTL_mskMPZIU ( 0x1 << MMU_CTL_offMPZIU )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define MMU_CTL_mskNTM0 ( 0x3 << MMU_CTL_offNTM0 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define MMU_CTL_mskNTM1 ( 0x3 << MMU_CTL_offNTM1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define MMU_CTL_mskNTM2 ( 0x3 << MMU_CTL_offNTM2 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define MMU_CTL_mskNTM3 ( 0x3 << MMU_CTL_offNTM3 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define MMU_CTL_D4KB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define MMU_CTL_D8KB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define MMU_CTL_UNA ( 0x1 << MMU_CTL_offUNA )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define MMU_CTL_CACHEABLE_NON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define MMU_CTL_CACHEABLE_WB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define MMU_CTL_CACHEABLE_WT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * mr1: L1_PPTB (L1 Physical Page Table Base Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define L1_PPTB_offNV 0 /* Enable Hardware Page Table Walker (HPTWK) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* bit 1:11 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define L1_PPTB_offBASE 12 /* First level physical page table base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define L1_PPTB_mskNV ( 0x1 << L1_PPTB_offNV )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define L1_PPTB_mskBASE ( 0xFFFFF << L1_PPTB_offBASE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * mr2: TLB_VPN (TLB Access VPN Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* bit 0:11 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define TLB_VPN_offVPN 12 /* Virtual Page Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define TLB_VPN_mskVPN ( 0xFFFFF << TLB_VPN_offVPN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * mr3: TLB_DATA (TLB Access Data Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define TLB_DATA_offV 0 /* PTE is valid and present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define TLB_DATA_offM 1 /* Page read/write access privilege */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define TLB_DATA_offD 4 /* Dirty bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define TLB_DATA_offX 5 /* Executable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define TLB_DATA_offA 6 /* Access bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define TLB_DATA_offG 7 /* Global page (shared across contexts) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define TLB_DATA_offC 8 /* Cacheability atribute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* bit 11:11 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define TLB_DATA_offPPN 12 /* Phisical Page Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define TLB_DATA_mskV ( 0x1 << TLB_DATA_offV )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define TLB_DATA_mskM ( 0x7 << TLB_DATA_offM )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define TLB_DATA_mskD ( 0x1 << TLB_DATA_offD )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define TLB_DATA_mskX ( 0x1 << TLB_DATA_offX )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define TLB_DATA_mskA ( 0x1 << TLB_DATA_offA )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define TLB_DATA_mskG ( 0x1 << TLB_DATA_offG )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define TLB_DATA_mskC ( 0x7 << TLB_DATA_offC )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define TLB_DATA_mskPPN ( 0xFFFFF << TLB_DATA_offPPN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define TLB_DATA_kernel_text_attr (TLB_DATA_mskV|TLB_DATA_mskM|TLB_DATA_mskD|TLB_DATA_mskX|TLB_DATA_mskG|TLB_DATA_mskC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define TLB_DATA_kernel_text_attr (TLB_DATA_mskV|TLB_DATA_mskM|TLB_DATA_mskD|TLB_DATA_mskX|TLB_DATA_mskG|(0x6 << TLB_DATA_offC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * mr4: TLB_MISC (TLB Access Misc Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define TLB_MISC_offACC_PSZ 0 /* Page size of a PTE entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define TLB_MISC_offCID 4 /* Context id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* bit 13:31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define TLB_MISC_mskACC_PSZ ( 0xF << TLB_MISC_offACC_PSZ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define TLB_MISC_mskCID ( 0x1FF << TLB_MISC_offCID )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * mr5: VLPT_IDX (Virtual Linear Page Table Index Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define VLPT_IDX_offZERO 0 /* Always 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define VLPT_IDX_offEVPN 2 /* Exception Virtual Page Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define VLPT_IDX_offVLPTB 22 /* Base VA of VLPT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define VLPT_IDX_mskZERO ( 0x3 << VLPT_IDX_offZERO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define VLPT_IDX_mskEVPN ( 0xFFFFF << VLPT_IDX_offEVPN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define VLPT_IDX_mskVLPTB ( 0x3FF << VLPT_IDX_offVLPTB )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * mr6: ILMB (Instruction Local Memory Base Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define ILMB_offIEN 0 /* Enable ILM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define ILMB_offILMSZ 1 /* Size of ILM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* bit 5:19 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define ILMB_offIBPA 20 /* Base PA of ILM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define ILMB_mskIEN ( 0x1 << ILMB_offIEN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define ILMB_mskILMSZ ( 0xF << ILMB_offILMSZ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define ILMB_mskIBPA ( 0xFFF << ILMB_offIBPA )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * mr7: DLMB (Data Local Memory Base Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define DLMB_offDEN 0 /* Enable DLM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define DLMB_offDLMSZ 1 /* Size of DLM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define DLMB_offDBM 5 /* Enable Double-Buffer Mode for DLM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define DLMB_offDBB 6 /* Double-buffer bank which can be accessed by the processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* bit 7:19 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define DLMB_offDBPA 20 /* Base PA of DLM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define DLMB_mskDEN ( 0x1 << DLMB_offDEN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define DLMB_mskDLMSZ ( 0xF << DLMB_offDLMSZ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define DLMB_mskDBM ( 0x1 << DLMB_offDBM )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define DLMB_mskDBB ( 0x1 << DLMB_offDBB )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define DLMB_mskDBPA ( 0xFFF << DLMB_offDBPA )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * mr8: CACHE_CTL (Cache Control Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define CACHE_CTL_offIC_EN 0 /* Enable I-cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define CACHE_CTL_offDC_EN 1 /* Enable D-cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define CACHE_CTL_offICALCK 2 /* I-cache all-lock resolution scheme */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define CACHE_CTL_offDCALCK 3 /* D-cache all-lock resolution scheme */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define CACHE_CTL_offDCCWF 4 /* Enable D-cache Critical Word Forwarding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define CACHE_CTL_offDCPMW 5 /* Enable D-cache concurrent miss and write-back processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* bit 6:31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define CACHE_CTL_mskIC_EN ( 0x1 << CACHE_CTL_offIC_EN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define CACHE_CTL_mskDC_EN ( 0x1 << CACHE_CTL_offDC_EN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define CACHE_CTL_mskICALCK ( 0x1 << CACHE_CTL_offICALCK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define CACHE_CTL_mskDCALCK ( 0x1 << CACHE_CTL_offDCALCK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define CACHE_CTL_mskDCCWF ( 0x1 << CACHE_CTL_offDCCWF )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define CACHE_CTL_mskDCPMW ( 0x1 << CACHE_CTL_offDCPMW )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * mr9: HSMP_SADDR (High Speed Memory Port Starting Address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define HSMP_SADDR_offEN 0 /* Enable control bit for the High Speed Memory port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* bit 1:19 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define HSMP_SADDR_offRANGE 1 /* Denote the address range (only defined in HSMP v2 ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define HSMP_SADDR_offSADDR 20 /* Starting base PA of the High Speed Memory Port region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define HSMP_SADDR_mskEN ( 0x1 << HSMP_SADDR_offEN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define HSMP_SADDR_mskRANGE ( 0xFFF << HSMP_SADDR_offRANGE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define HSMP_SADDR_mskSADDR ( 0xFFF << HSMP_SADDR_offSADDR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * mr10: HSMP_EADDR (High Speed Memory Port Ending Address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* bit 0:19 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define HSMP_EADDR_offEADDR 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define HSMP_EADDR_mskEADDR ( 0xFFF << HSMP_EADDR_offEADDR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * dr0+(n*5): BPCn (n=0-7) (Breakpoint Control Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define BPC_offWP 0 /* Configuration of BPAn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define BPC_offEL 1 /* Enable BPAn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define BPC_offS 2 /* Data address comparison for a store instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define BPC_offP 3 /* Compared data address is PA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define BPC_offC 4 /* CID value is compared with the BPCIDn register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define BPC_offBE0 5 /* Enable byte mask for the comparison with register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define BPC_offBE1 6 /* Enable byte mask for the comparison with register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define BPC_offBE2 7 /* Enable byte mask for the comparison with register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define BPC_offBE3 8 /* Enable byte mask for the comparison with register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define BPC_offT 9 /* Enable breakpoint Embedded Tracer triggering operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define BPC_mskWP ( 0x1 << BPC_offWP )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define BPC_mskEL ( 0x1 << BPC_offEL )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define BPC_mskS ( 0x1 << BPC_offS )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define BPC_mskP ( 0x1 << BPC_offP )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define BPC_mskC ( 0x1 << BPC_offC )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define BPC_mskBE0 ( 0x1 << BPC_offBE0 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define BPC_mskBE1 ( 0x1 << BPC_offBE1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define BPC_mskBE2 ( 0x1 << BPC_offBE2 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define BPC_mskBE3 ( 0x1 << BPC_offBE3 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define BPC_mskT ( 0x1 << BPC_offT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * dr1+(n*5): BPAn (n=0-7) (Breakpoint Address Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* These registers contain break point address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * dr2+(n*5): BPAMn (n=0-7) (Breakpoint Address Mask Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* These registerd contain the address comparison mask for the BPAn register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * dr3+(n*5): BPVn (n=0-7) Breakpoint Data Value Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* The BPVn register contains the data value that will be compared with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * incoming load/store data value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * dr4+(n*5): BPCIDn (n=0-7) (Breakpoint Context ID Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define BPCID_offCID 0 /* CID that will be compared with a process's CID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* bit 9:31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define BPCID_mskCID ( 0x1FF << BPCID_offCID )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * dr40: EDM_CFG (EDM Configuration Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define EDM_CFG_offBC 0 /* Number of hardware breakpoint sets implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define EDM_CFG_offDIMU 3 /* Debug Instruction Memory Unit exists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* bit 4:15 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define EDM_CFG_offVER 16 /* EDM version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define EDM_CFG_mskBC ( 0x7 << EDM_CFG_offBC )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define EDM_CFG_mskDIMU ( 0x1 << EDM_CFG_offDIMU )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define EDM_CFG_mskVER ( 0xFFFF << EDM_CFG_offVER )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * dr41: EDMSW (EDM Status Word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define EDMSW_offWV 0 /* Write Valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define EDMSW_offRV 1 /* Read Valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define EDMSW_offDE 2 /* Debug exception has occurred for this core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* bit 3:31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define EDMSW_mskWV ( 0x1 << EDMSW_offWV )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define EDMSW_mskRV ( 0x1 << EDMSW_offRV )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define EDMSW_mskDE ( 0x1 << EDMSW_offDE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * dr42: EDM_CTL (EDM Control Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* bit 0:30 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define EDM_CTL_offV3_EDM_MODE 6 /* EDM compatibility control bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define EDM_CTL_offDEH_SEL 31 /* Controls where debug exception is directed to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define EDM_CTL_mskV3_EDM_MODE ( 0x1 << EDM_CTL_offV3_EDM_MODE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define EDM_CTL_mskDEH_SEL ( 0x1 << EDM_CTL_offDEH_SEL )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * dr43: EDM_DTR (EDM Data Transfer Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* This is used to exchange data between the embedded EDM logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * and the processor core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * dr44: BPMTC (Breakpoint Match Trigger Counter Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define BPMTC_offBPMTC 0 /* Breakpoint match trigger counter value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* bit 16:31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define BPMTC_mskBPMTC ( 0xFFFF << BPMTC_offBPMTC )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * dr45: DIMBR (Debug Instruction Memory Base Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* bit 0:11 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define DIMBR_offDIMB 12 /* Base address of the Debug Instruction Memory (DIM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define DIMBR_mskDIMB ( 0xFFFFF << DIMBR_offDIMB )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * dr46: TECR0(Trigger Event Control register 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * dr47: TECR1 (Trigger Event Control register 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define TECR_offBP 0 /* Controld which BP is used as a trigger source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define TECR_offNMI 8 /* Use NMI as a trigger source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define TECR_offHWINT 9 /* Corresponding interrupt is used as a trigger source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define TECR_offEVIC 15 /* Enable HWINT as a trigger source in EVIC mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define TECR_offSYS 16 /* Enable SYSCALL instruction as a trigger source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define TECR_offDBG 17 /* Enable debug exception as a trigger source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define TECR_offMRE 18 /* Enable MMU related exception as a trigger source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define TECR_offE 19 /* An exception is used as a trigger source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* bit 20:30 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define TECR_offL 31 /* Link/Cascade TECR0 trigger event to TECR1 trigger event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define TECR_mskBP ( 0xFF << TECR_offBP )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define TECR_mskNMI ( 0x1 << TECR_offBNMI )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define TECR_mskHWINT ( 0x3F << TECR_offBHWINT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define TECR_mskEVIC ( 0x1 << TECR_offBEVIC )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define TECR_mskSYS ( 0x1 << TECR_offBSYS )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define TECR_mskDBG ( 0x1 << TECR_offBDBG )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define TECR_mskMRE ( 0x1 << TECR_offBMRE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define TECR_mskE ( 0x1 << TECR_offE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define TECR_mskL ( 0x1 << TECR_offL )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * pfr0-2: PFMC0-2 (Performance Counter Register 0-2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* These registers contains performance event count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * pfr3: PFM_CTL (Performance Counter Control Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define PFM_CTL_offEN0 0 /* Enable PFMC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define PFM_CTL_offEN1 1 /* Enable PFMC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define PFM_CTL_offEN2 2 /* Enable PFMC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define PFM_CTL_offIE0 3 /* Enable interrupt for PFMC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define PFM_CTL_offIE1 4 /* Enable interrupt for PFMC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define PFM_CTL_offIE2 5 /* Enable interrupt for PFMC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define PFM_CTL_offOVF0 6 /* Overflow bit of PFMC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define PFM_CTL_offOVF1 7 /* Overflow bit of PFMC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define PFM_CTL_offOVF2 8 /* Overflow bit of PFMC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define PFM_CTL_offKS0 9 /* Enable superuser mode event counting for PFMC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define PFM_CTL_offKS1 10 /* Enable superuser mode event counting for PFMC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define PFM_CTL_offKS2 11 /* Enable superuser mode event counting for PFMC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define PFM_CTL_offKU0 12 /* Enable user mode event counting for PFMC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define PFM_CTL_offKU1 13 /* Enable user mode event counting for PFMC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define PFM_CTL_offKU2 14 /* Enable user mode event counting for PFMC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define PFM_CTL_offSEL0 15 /* The event selection for PFMC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define PFM_CTL_offSEL1 16 /* The event selection for PFMC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define PFM_CTL_offSEL2 22 /* The event selection for PFMC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* bit 28:31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define PFM_CTL_mskEN0 ( 0x01 << PFM_CTL_offEN0 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define PFM_CTL_mskEN1 ( 0x01 << PFM_CTL_offEN1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define PFM_CTL_mskEN2 ( 0x01 << PFM_CTL_offEN2 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define PFM_CTL_mskIE0 ( 0x01 << PFM_CTL_offIE0 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define PFM_CTL_mskIE1 ( 0x01 << PFM_CTL_offIE1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define PFM_CTL_mskIE2 ( 0x01 << PFM_CTL_offIE2 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define PFM_CTL_mskOVF0 ( 0x01 << PFM_CTL_offOVF0 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define PFM_CTL_mskOVF1 ( 0x01 << PFM_CTL_offOVF1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define PFM_CTL_mskOVF2 ( 0x01 << PFM_CTL_offOVF2 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define PFM_CTL_mskKS0 ( 0x01 << PFM_CTL_offKS0 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define PFM_CTL_mskKS1 ( 0x01 << PFM_CTL_offKS1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define PFM_CTL_mskKS2 ( 0x01 << PFM_CTL_offKS2 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define PFM_CTL_mskKU0 ( 0x01 << PFM_CTL_offKU0 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define PFM_CTL_mskKU1 ( 0x01 << PFM_CTL_offKU1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define PFM_CTL_mskKU2 ( 0x01 << PFM_CTL_offKU2 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define PFM_CTL_mskSEL0 ( 0x01 << PFM_CTL_offSEL0 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define PFM_CTL_mskSEL1 ( 0x3F << PFM_CTL_offSEL1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define PFM_CTL_mskSEL2 ( 0x3F << PFM_CTL_offSEL2 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * SDZ_CTL (Structure Downsizing Control Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define SDZ_CTL_offICDZ 0 /* I-cache downsizing control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define SDZ_CTL_offDCDZ 3 /* D-cache downsizing control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define SDZ_CTL_offMTBDZ 6 /* MTLB downsizing control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define SDZ_CTL_offBTBDZ 9 /* Branch Target Table downsizing control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* bit 12:31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define SDZ_CTL_mskICDZ ( 0x07 << SDZ_CTL_offICDZ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define SDZ_CTL_mskDCDZ ( 0x07 << SDZ_CTL_offDCDZ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define SDZ_CTL_mskMTBDZ ( 0x07 << SDZ_CTL_offMTBDZ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define SDZ_CTL_mskBTBDZ ( 0x07 << SDZ_CTL_offBTBDZ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * N13MISC_CTL (N13 Miscellaneous Control Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define N13MISC_CTL_offBTB 0 /* Disable Branch Target Buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define N13MISC_CTL_offRTP 1 /* Disable Return Target Predictor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define N13MISC_CTL_offPTEPF 2 /* Disable HPTWK L2 PTE pefetch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define N13MISC_CTL_offSP_SHADOW_EN 4 /* Enable shadow stack pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define MISC_CTL_offHWPRE 11 /* Enable HardWare PREFETCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* bit 6, 9:31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define N13MISC_CTL_makBTB ( 0x1 << N13MISC_CTL_offBTB )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define N13MISC_CTL_makRTP ( 0x1 << N13MISC_CTL_offRTP )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define N13MISC_CTL_makPTEPF ( 0x1 << N13MISC_CTL_offPTEPF )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define N13MISC_CTL_makSP_SHADOW_EN ( 0x1 << N13MISC_CTL_offSP_SHADOW_EN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define MISC_CTL_makHWPRE_EN ( 0x1 << MISC_CTL_offHWPRE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #ifdef CONFIG_HW_PRE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define MISC_init (N13MISC_CTL_makBTB|N13MISC_CTL_makRTP|N13MISC_CTL_makSP_SHADOW_EN|MISC_CTL_makHWPRE_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define MISC_init (N13MISC_CTL_makBTB|N13MISC_CTL_makRTP|N13MISC_CTL_makSP_SHADOW_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * PRUSR_ACC_CTL (Privileged Resource User Access Control Registers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define PRUSR_ACC_CTL_offDMA_EN 0 /* Allow user mode access of DMA registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define PRUSR_ACC_CTL_offPFM_EN 1 /* Allow user mode access of PFM registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define PRUSR_ACC_CTL_mskDMA_EN ( 0x1 << PRUSR_ACC_CTL_offDMA_EN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define PRUSR_ACC_CTL_mskPFM_EN ( 0x1 << PRUSR_ACC_CTL_offPFM_EN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * dmar0: DMA_CFG (DMA Configuration Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define DMA_CFG_offNCHN 0 /* The number of DMA channels implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define DMA_CFG_offUNEA 2 /* Un-aligned External Address transfer feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define DMA_CFG_off2DET 3 /* 2-D Element Transfer feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* bit 4:15 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define DMA_CFG_offVER 16 /* DMA architecture and implementation version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define DMA_CFG_mskNCHN ( 0x3 << DMA_CFG_offNCHN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define DMA_CFG_mskUNEA ( 0x1 << DMA_CFG_offUNEA )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define DMA_CFG_msk2DET ( 0x1 << DMA_CFG_off2DET )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define DMA_CFG_mskVER ( 0xFFFF << DMA_CFG_offVER )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * dmar1: DMA_GCSW (DMA Global Control and Status Word Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define DMA_GCSW_offC0STAT 0 /* DMA channel 0 state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define DMA_GCSW_offC1STAT 3 /* DMA channel 1 state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* bit 6:11 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define DMA_GCSW_offC0INT 12 /* DMA channel 0 generate interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define DMA_GCSW_offC1INT 13 /* DMA channel 1 generate interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* bit 14:30 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define DMA_GCSW_offEN 31 /* Enable DMA engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define DMA_GCSW_mskC0STAT ( 0x7 << DMA_GCSW_offC0STAT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define DMA_GCSW_mskC1STAT ( 0x7 << DMA_GCSW_offC1STAT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define DMA_GCSW_mskC0INT ( 0x1 << DMA_GCSW_offC0INT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define DMA_GCSW_mskC1INT ( 0x1 << DMA_GCSW_offC1INT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define DMA_GCSW_mskEN ( 0x1 << DMA_GCSW_offEN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * dmar2: DMA_CHNSEL (DMA Channel Selection Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define DMA_CHNSEL_offCHAN 0 /* Selected channel number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* bit 2:31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define DMA_CHNSEL_mskCHAN ( 0x3 << DMA_CHNSEL_offCHAN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * dmar3: DMA_ACT (DMA Action Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define DMA_ACT_offACMD 0 /* DMA Action Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* bit 2:31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define DMA_ACT_mskACMD ( 0x3 << DMA_ACT_offACMD )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * dmar4: DMA_SETUP (DMA Setup Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define DMA_SETUP_offLM 0 /* Local Memory Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define DMA_SETUP_offTDIR 1 /* Transfer Direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define DMA_SETUP_offTES 2 /* Transfer Element Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define DMA_SETUP_offESTR 4 /* External memory transfer Stride */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define DMA_SETUP_offCIE 16 /* Interrupt Enable on Completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define DMA_SETUP_offSIE 17 /* Interrupt Enable on explicit Stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define DMA_SETUP_offEIE 18 /* Interrupt Enable on Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define DMA_SETUP_offUE 19 /* Enable the Un-aligned External Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define DMA_SETUP_off2DE 20 /* Enable the 2-D External Transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define DMA_SETUP_offCOA 21 /* Transfer Coalescable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* bit 22:31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define DMA_SETUP_mskLM ( 0x1 << DMA_SETUP_offLM )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define DMA_SETUP_mskTDIR ( 0x1 << DMA_SETUP_offTDIR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define DMA_SETUP_mskTES ( 0x3 << DMA_SETUP_offTES )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define DMA_SETUP_mskESTR ( 0xFFF << DMA_SETUP_offESTR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define DMA_SETUP_mskCIE ( 0x1 << DMA_SETUP_offCIE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define DMA_SETUP_mskSIE ( 0x1 << DMA_SETUP_offSIE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define DMA_SETUP_mskEIE ( 0x1 << DMA_SETUP_offEIE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define DMA_SETUP_mskUE ( 0x1 << DMA_SETUP_offUE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define DMA_SETUP_msk2DE ( 0x1 << DMA_SETUP_off2DE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define DMA_SETUP_mskCOA ( 0x1 << DMA_SETUP_offCOA )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * dmar5: DMA_ISADDR (DMA Internal Start Address Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define DMA_ISADDR_offISADDR 0 /* Internal Start Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* bit 20:31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define DMA_ISADDR_mskISADDR ( 0xFFFFF << DMA_ISADDR_offISADDR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * dmar6: DMA_ESADDR (DMA External Start Address Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* This register holds External Start Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * dmar7: DMA_TCNT (DMA Transfer Element Count Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define DMA_TCNT_offTCNT 0 /* DMA transfer element count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* bit 18:31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define DMA_TCNT_mskTCNT ( 0x3FFFF << DMA_TCNT_offTCNT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * dmar8: DMA_STATUS (DMA Status Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define DMA_STATUS_offSTAT 0 /* DMA channel state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define DMA_STATUS_offSTUNA 3 /* Un-aligned error on External Stride value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define DMA_STATUS_offDERR 4 /* DMA Transfer Disruption Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define DMA_STATUS_offEUNA 5 /* Un-aligned error on the External address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define DMA_STATUS_offIUNA 6 /* Un-aligned error on the Internal address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define DMA_STATUS_offIOOR 7 /* Out-Of-Range error on the Internal address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define DMA_STATUS_offEBUS 8 /* Bus Error on an External DMA transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define DMA_STATUS_offESUP 9 /* DMA setup error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* bit 10:31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define DMA_STATUS_mskSTAT ( 0x7 << DMA_STATUS_offSTAT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define DMA_STATUS_mskSTUNA ( 0x1 << DMDMA_STATUS_offSTUNA )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define DMA_STATUS_mskDERR ( 0x1 << DMDMA_STATUS_offDERR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define DMA_STATUS_mskEUNA ( 0x1 << DMDMA_STATUS_offEUNA )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define DMA_STATUS_mskIUNA ( 0x1 << DMDMA_STATUS_offIUNA )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define DMA_STATUS_mskIOOR ( 0x1 << DMDMA_STATUS_offIOOR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define DMA_STATUS_mskEBUS ( 0x1 << DMDMA_STATUS_offEBUS )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define DMA_STATUS_mskESUP ( 0x1 << DMDMA_STATUS_offESUP )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * dmar9: DMA_2DSET (DMA 2D Setup Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define DMA_2DSET_offWECNT 0 /* The Width Element Count for a 2-D region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define DMA_2DSET_offHTSTR 16 /* The Height Stride for a 2-D region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define DMA_2DSET_mskHTSTR ( 0xFFFF << DMA_2DSET_offHTSTR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define DMA_2DSET_mskWECNT ( 0xFFFF << DMA_2DSET_offWECNT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * dmar10: DMA_2DSCTL (DMA 2D Startup Control Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define DMA_2DSCTL_offSTWECNT 0 /* Startup Width Element Count for a 2-D region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /* bit 16:31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define DMA_2DSCTL_mskSTWECNT ( 0xFFFF << DMA_2DSCTL_offSTWECNT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * fpcsr: FPCSR (Floating-Point Control Status Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define FPCSR_offRM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define FPCSR_offIVO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define FPCSR_offDBZ 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define FPCSR_offOVF 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define FPCSR_offUDF 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define FPCSR_offIEX 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define FPCSR_offIVOE 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define FPCSR_offDBZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define FPCSR_offOVFE 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define FPCSR_offUDFE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define FPCSR_offIEXE 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define FPCSR_offDNZ 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define FPCSR_offIVOT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define FPCSR_offDBZT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define FPCSR_offOVFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define FPCSR_offUDFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define FPCSR_offIEXT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define FPCSR_offDNIT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define FPCSR_offRIT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define FPCSR_mskRM ( 0x3 << FPCSR_offRM )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define FPCSR_mskIVO ( 0x1 << FPCSR_offIVO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define FPCSR_mskDBZ ( 0x1 << FPCSR_offDBZ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define FPCSR_mskOVF ( 0x1 << FPCSR_offOVF )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define FPCSR_mskUDF ( 0x1 << FPCSR_offUDF )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define FPCSR_mskIEX ( 0x1 << FPCSR_offIEX )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define FPCSR_mskIVOE ( 0x1 << FPCSR_offIVOE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define FPCSR_mskDBZE ( 0x1 << FPCSR_offDBZE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define FPCSR_mskOVFE ( 0x1 << FPCSR_offOVFE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define FPCSR_mskUDFE ( 0x1 << FPCSR_offUDFE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define FPCSR_mskIEXE ( 0x1 << FPCSR_offIEXE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define FPCSR_mskDNZ ( 0x1 << FPCSR_offDNZ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define FPCSR_mskIVOT ( 0x1 << FPCSR_offIVOT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define FPCSR_mskDBZT ( 0x1 << FPCSR_offDBZT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define FPCSR_mskOVFT ( 0x1 << FPCSR_offOVFT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define FPCSR_mskUDFT ( 0x1 << FPCSR_offUDFT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define FPCSR_mskIEXT ( 0x1 << FPCSR_offIEXT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define FPCSR_mskDNIT ( 0x1 << FPCSR_offDNIT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define FPCSR_mskRIT ( 0x1 << FPCSR_offRIT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define FPCSR_mskALL (FPCSR_mskIVO | FPCSR_mskDBZ | FPCSR_mskOVF | FPCSR_mskUDF | FPCSR_mskIEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define FPCSR_mskALLE_NO_UDF_IEXE (FPCSR_mskIVOE | FPCSR_mskDBZE | FPCSR_mskOVFE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define FPCSR_mskALLE (FPCSR_mskIVOE | FPCSR_mskDBZE | FPCSR_mskOVFE | FPCSR_mskUDFE | FPCSR_mskIEXE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define FPCSR_mskALLT (FPCSR_mskIVOT | FPCSR_mskDBZT | FPCSR_mskOVFT | FPCSR_mskUDFT | FPCSR_mskIEXT |FPCSR_mskDNIT | FPCSR_mskRIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) * fpcfg: FPCFG (Floating-Point Configuration Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define FPCFG_offSP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define FPCFG_offDP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define FPCFG_offFREG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define FPCFG_offFMA 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define FPCFG_offIMVER 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define FPCFG_offAVER 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define FPCFG_mskSP ( 0x1 << FPCFG_offSP )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define FPCFG_mskDP ( 0x1 << FPCFG_offDP )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define FPCFG_mskFREG ( 0x3 << FPCFG_offFREG )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define FPCFG_mskFMA ( 0x1 << FPCFG_offFMA )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define FPCFG_mskIMVER ( 0x1F << FPCFG_offIMVER )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define FPCFG_mskAVER ( 0x1F << FPCFG_offAVER )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* 8 Single precision or 4 double precision registers are available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define SP8_DP4_reg 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /* 16 Single precision or 8 double precision registers are available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define SP16_DP8_reg 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* 32 Single precision or 16 double precision registers are available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define SP32_DP16_reg 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /* 32 Single precision or 32 double precision registers are available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define SP32_DP32_reg 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * fucpr: FUCOP_CTL (FPU and Coprocessor Enable Control Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #define FUCOP_CTL_offCP0EN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #define FUCOP_CTL_offCP1EN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #define FUCOP_CTL_offCP2EN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define FUCOP_CTL_offCP3EN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #define FUCOP_CTL_offAUEN 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define FUCOP_CTL_mskCP0EN ( 0x1 << FUCOP_CTL_offCP0EN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #define FUCOP_CTL_mskCP1EN ( 0x1 << FUCOP_CTL_offCP1EN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #define FUCOP_CTL_mskCP2EN ( 0x1 << FUCOP_CTL_offCP2EN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #define FUCOP_CTL_mskCP3EN ( 0x1 << FUCOP_CTL_offCP3EN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define FUCOP_CTL_mskAUEN ( 0x1 << FUCOP_CTL_offAUEN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #endif /* __NDS32_BITFIELD_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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