Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /dts-v1/;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 	compatible = "andestech,ae3xx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	interrupt-parent = <&intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 	chosen {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 		stdout-path = &serial0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	memory@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 		device_type = "memory";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 		reg = <0x00000000 0x40000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 			device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 			compatible = "andestech,n13", "andestech,nds32v3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 			reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 			clock-frequency = <60000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 			next-level-cache = <&L2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	intc: interrupt-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		compatible = "andestech,ativic32";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	clock: clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		clock-frequency = <30000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	apb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		compatible = "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		serial0: serial@f0300000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 			compatible = "andestech,uart16550", "ns16550a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 			reg = <0xf0300000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 			interrupts = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 			clock-frequency = <14745600>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			reg-shift = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			reg-offset = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			no-loopback-test = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		timer0: timer@f0400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 			compatible = "andestech,atcpit100";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 			reg = <0xf0400000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 			interrupts = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 			clocks = <&clock>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 			clock-names = "PCLK";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	ahb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		compatible = "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 		#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 		ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 		L2: cache-controller@e0500000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 			compatible = "andestech,atl2c";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 			reg = <0xe0500000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 			cache-unified;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 			cache-level = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 		mac0: ethernet@e0100000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 			compatible = "andestech,atmac100";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 			reg = <0xe0100000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 			interrupts = <18>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 	pmu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 		compatible = "andestech,nds32v3-pmu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 		interrupts= <13>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };