Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) # SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) comment "Processor Features"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) config CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 	def_bool !CPU_LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) config CPU_LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 	bool "Little endian"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 	default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) config FPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 	bool "FPU support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 	default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	  If FPU ISA is used in user space, this configuration shall be Y to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)           enable required support in kernel such as fpu context switch and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)           fpu exception handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	  If no FPU ISA is used in user space, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) config LAZY_FPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	bool "lazy FPU support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	depends on FPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	  Say Y here to enable the lazy FPU scheme. The lazy FPU scheme can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)           enhance system performance by reducing the context switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	  frequency of the FPU register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	  For normal case, say Y.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) config SUPPORT_DENORMAL_ARITHMETIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	bool "Denormal arithmetic support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	depends on FPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	  Say Y here to enable arithmetic of denormalized number. Enabling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	  this feature can enhance the precision for tininess number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	  However, performance loss in float point calculations is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	  possibly significant due to additional FPU exception.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	  If the calculated tolerance for tininess number is not critical,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	  say N to prevent performance loss.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) config HWZOL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	bool "hardware zero overhead loop support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	depends on CPU_D10 || CPU_D15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	  A set of Zero-Overhead Loop mechanism is provided to reduce the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	  instruction fetch and execution overhead of loop-control instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	  It will save 3 registers($LB, $LC, $LE) for context saving if say Y.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	  You don't need to save these registers if you can make sure your user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	  program doesn't use these registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	  If unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) config CPU_CACHE_ALIASING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	bool "Aliasing cache"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	depends on CPU_N10 || CPU_D10 || CPU_N13 || CPU_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	  If this CPU is using VIPT data cache and its cache way size is larger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	  than page size, say Y. If it is using PIPT data cache, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	  If unsure, say Y.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) choice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	prompt "minimum CPU type"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	default CPU_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	  The data cache of N15/D15 is implemented as PIPT and it will not cause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	  the cache aliasing issue. The rest cpus(N13, N10 and D10) are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	  implemented as VIPT data cache. It may cause the cache aliasing issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	  if its cache way size is larger than page size. You can specify the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	  CPU type directly or choose CPU_V3 if unsure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)           A kernel built for N10 is able to run on N15, D15, N13, N10 or D10.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)           A kernel built for N15 is able to run on N15 or D15.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)           A kernel built for D10 is able to run on D10 or D15.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)           A kernel built for D15 is able to run on D15.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)           A kernel built for N13 is able to run on N15, N13 or D15.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) config CPU_N15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	bool "AndesCore N15"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) config CPU_N13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	bool "AndesCore N13"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) config CPU_N10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	bool "AndesCore N10"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	select CPU_CACHE_ALIASING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) config CPU_D15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	bool "AndesCore D15"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) config CPU_D10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	bool "AndesCore D10"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	select CPU_CACHE_ALIASING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) config CPU_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	bool "AndesCore v3 compatible"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	select CPU_CACHE_ALIASING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) endchoice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) choice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	prompt "Paging -- page size "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	default ANDES_PAGE_SIZE_4KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) config  ANDES_PAGE_SIZE_4KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	bool "use 4KB page size"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) config  ANDES_PAGE_SIZE_8KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	bool "use 8KB page size"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) endchoice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) config CPU_ICACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	bool "Disable I-Cache"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	  Say Y here to disable the processor instruction cache. Unless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	  you have a reason not to or are unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) config CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	bool "Disable D-Cache"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	  Say Y here to disable the processor data cache. Unless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	  you have a reason not to or are unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) config CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	bool "Force write through D-cache"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	depends on !CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	  Say Y here to use the data cache in writethrough mode. Unless you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	  specifically require this or are unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) config WBNA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	bool "WBNA"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	  Say Y here to enable write-back memory with no-write-allocation policy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) config ALIGNMENT_TRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	bool "Kernel support unaligned access handling by sw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	depends on PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	  Andes processors cannot load/store information which is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	  naturally aligned on the bus, i.e., a 4 byte load must start at an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	  address divisible by 4. On 32-bit Andes processors, these non-aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	  load/store instructions will be emulated in software if you say Y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	  here, which has a severe performance impact. With an IP-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	  configuration it is safe to say N, otherwise say Y.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) config HW_SUPPORT_UNALIGNMENT_ACCESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	bool "Kernel support unaligned access handling by hw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	depends on !ALIGNMENT_TRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	  Andes processors load/store world/half-word instructions can access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	  unaligned memory locations without generating the Data Alignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	  Check exceptions. With an IP-only configuration it is safe to say N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	  otherwise say Y.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) config HIGHMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	bool "High Memory Support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	depends on MMU && !CPU_CACHE_ALIASING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	  The address space of Andes processors is only 4 Gigabytes large
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	  and it has to accommodate user address space, kernel address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	  space as well as some memory mapped IO. That means that, if you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	  have a large amount of physical memory and/or IO, not all of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	  memory can be "permanently mapped" by the kernel. The physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	  memory that is not permanently mapped is called "high memory".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	  Depending on the selected kernel/user memory split, minimum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	  vmalloc space and actual amount of RAM, you may not need this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	  option which should result in a slightly faster kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	  If unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) config CACHE_L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	bool "Support L2 cache"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)         default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	  Say Y here to enable L2 cache if your SoC are integrated with L2CC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	  If unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) config HW_PRE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	bool "Enable hardware prefetcher"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	  Say Y here to enable hardware prefetcher feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	  Only when CPU_VER.REV >= 0x09 can support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) menu "Memory configuration"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) choice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	prompt "Memory split"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	depends on MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	default VMSPLIT_3G_OPT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	  Select the desired split between kernel and user memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	  If you are not absolutely sure what you are doing, leave this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	  option alone!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	config VMSPLIT_3G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		bool "3G/1G user/kernel split"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	config VMSPLIT_3G_OPT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		bool "3G/1G user/kernel split (for full 1G low memory)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	config VMSPLIT_2G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		bool "2G/2G user/kernel split"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	config VMSPLIT_1G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		bool "1G/3G user/kernel split"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) endchoice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) config PAGE_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	hex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	default 0x40000000 if VMSPLIT_1G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	default 0x80000000 if VMSPLIT_2G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	default 0xB0000000 if VMSPLIT_3G_OPT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	default 0xC0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) endmenu