^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * NEC VR4100 series SIU platform device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007-2008 Yoichi Yuasa <yuasa@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/vr41xx/siu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static unsigned int siu_type1_ports[SIU_PORTS_MAX] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) PORT_VR41XX_SIU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) PORT_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static struct resource siu_type1_resource[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .start = 0x0c000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .end = 0x0c00000a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .start = SIU_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .end = SIU_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static unsigned int siu_type2_ports[SIU_PORTS_MAX] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PORT_VR41XX_SIU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PORT_VR41XX_DSIU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static struct resource siu_type2_resource[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .start = 0x0f000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .end = 0x0f00080a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .start = 0x0f000820,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .end = 0x0f000829,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .start = SIU_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .end = SIU_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .start = DSIU_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .end = DSIU_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int __init vr41xx_siu_add(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) pdev = platform_device_alloc("SIU", -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (!pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) switch (current_cpu_type()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) case CPU_VR4111:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) case CPU_VR4121:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pdev->dev.platform_data = siu_type1_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) res = siu_type1_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) num = ARRAY_SIZE(siu_type1_resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) case CPU_VR4122:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) case CPU_VR4131:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) case CPU_VR4133:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) pdev->dev.platform_data = siu_type2_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) res = siu_type2_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) num = ARRAY_SIZE(siu_type2_resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) goto err_free_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) retval = platform_device_add_resources(pdev, res, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) goto err_free_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) retval = platform_device_add(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) goto err_free_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) err_free_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) platform_device_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) device_initcall(vr41xx_siu_add);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) void __init vr41xx_siu_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int *type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) switch (current_cpu_type()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) case CPU_VR4111:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) case CPU_VR4121:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) type = siu_type1_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) res = siu_type1_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) case CPU_VR4122:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) case CPU_VR4131:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) case CPU_VR4133:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) type = siu_type2_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) res = siu_type2_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) for (i = 0; i < SIU_PORTS_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) port.line = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) port.type = type[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (port.type == PORT_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) port.mapbase = res[i].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) port.membase = (unsigned char __iomem *)KSEG1ADDR(res[i].start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) vr41xx_siu_early_setup(&port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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