^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Interrupt handing routines for NEC VR4100 series.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005-2007 Yoichi Yuasa <yuasa@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/irq_cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/vr41xx/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) typedef struct irq_cascade {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) int (*get_irq)(unsigned int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) } irq_cascade_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static irq_cascade_t irq_cascade[NR_IRQS] __cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) if (irq >= NR_IRQS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) if (irq_cascade[irq].get_irq != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) free_irq(irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) irq_cascade[irq].get_irq = get_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) if (get_irq != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) retval = request_irq(irq, no_action, IRQF_NO_THREAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) "cascade", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) irq_cascade[irq].get_irq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) EXPORT_SYMBOL_GPL(cascade_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static void irq_dispatch(unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) irq_cascade_t *cascade;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (irq >= NR_IRQS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) atomic_inc(&irq_err_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) cascade = irq_cascade + irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (cascade->get_irq != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct irq_desc *desc = irq_to_desc(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct irq_data *idata = irq_desc_get_irq_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (chip->irq_mask_ack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) chip->irq_mask_ack(idata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) chip->irq_mask(idata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) chip->irq_ack(idata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ret = cascade->get_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) atomic_inc(&irq_err_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) irq_dispatch(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (!irqd_irq_disabled(idata) && chip->irq_unmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) chip->irq_unmask(idata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) do_IRQ(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) asmlinkage void plat_irq_dispatch(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (pending & CAUSEF_IP7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) do_IRQ(TIMER_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) else if (pending & 0x7800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (pending & CAUSEF_IP3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) irq_dispatch(INT1_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) else if (pending & CAUSEF_IP4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) irq_dispatch(INT2_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) else if (pending & CAUSEF_IP5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) irq_dispatch(INT3_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) else if (pending & CAUSEF_IP6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) irq_dispatch(INT4_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) } else if (pending & CAUSEF_IP2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) irq_dispatch(INT0_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) else if (pending & CAUSEF_IP0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) do_IRQ(MIPS_SOFTINT0_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) else if (pending & CAUSEF_IP1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) do_IRQ(MIPS_SOFTINT1_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) spurious_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) void __init arch_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) mips_cpu_irq_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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