^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * icu.c, Interrupt Control Unit routines for the NEC VR4100 series.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2001-2002 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Yoichi Yuasa <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2003-2006 Yoichi Yuasa <yuasa@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Changes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * MontaVista Software Inc. <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * - New creation, NEC VR4122 and VR4131 are supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * - Added support for NEC VR4111 and VR4121.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Yoichi Yuasa <yuasa@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * - Coped with INTASSIGN of NEC VR4133.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/vr41xx/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/vr41xx/vr41xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static void __iomem *icu1_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static void __iomem *icu2_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static unsigned char sysint1_assign[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static unsigned char sysint2_assign[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ICU1_TYPE1_BASE 0x0b000080UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ICU2_TYPE1_BASE 0x0b000200UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ICU1_TYPE2_BASE 0x0f000080UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ICU2_TYPE2_BASE 0x0f0000a0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ICU1_SIZE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ICU2_SIZE 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SYSINT1REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PIUINTREG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define INTASSIGN0 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define INTASSIGN1 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GIUINTLREG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DSIUINTREG 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MSYSINT1REG 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MPIUINTREG 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MAIUINTREG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MKIUINTREG 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MMACINTREG 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MGIUINTLREG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MDSIUINTREG 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define NMIREG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SOFTREG 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define INTASSIGN2 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define INTASSIGN3 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SYSINT2REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GIUINTHREG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define FIRINTREG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MSYSINT2REG 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MGIUINTHREG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MFIRINTREG 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PCIINTREG 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PCIINT0 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SCUINTREG 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SCUINT0 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CSIINTREG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MPCIINTREG 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MSCUINTREG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MCSIINTREG 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define BCUINTREG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define BCUINTR 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MBCUINTREG 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SYSINT1_IRQ_TO_PIN(x) ((x) - SYSINT1_IRQ_BASE) /* Pin 0-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SYSINT2_IRQ_TO_PIN(x) ((x) - SYSINT2_IRQ_BASE) /* Pin 0-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define INT_TO_IRQ(x) ((x) + 2) /* Int0-4 -> IRQ2-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define icu1_read(offset) readw(icu1_base + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define icu1_write(offset, value) writew((value), icu1_base + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define icu2_read(offset) readw(icu2_base + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define icu2_write(offset, value) writew((value), icu2_base + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define INTASSIGN_MAX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define INTASSIGN_MASK 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static inline uint16_t icu1_set(uint8_t offset, uint16_t set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) uint16_t data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) data = icu1_read(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) data |= set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) icu1_write(offset, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static inline uint16_t icu1_clear(uint8_t offset, uint16_t clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) uint16_t data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) data = icu1_read(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) data &= ~clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) icu1_write(offset, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static inline uint16_t icu2_set(uint8_t offset, uint16_t set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) uint16_t data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) data = icu2_read(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) data |= set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) icu2_write(offset, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static inline uint16_t icu2_clear(uint8_t offset, uint16_t clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) uint16_t data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) data = icu2_read(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) data &= ~clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) icu2_write(offset, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) void vr41xx_enable_piuint(uint16_t mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct irq_desc *desc = irq_to_desc(PIU_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (current_cpu_type() == CPU_VR4111 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) current_cpu_type() == CPU_VR4121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) raw_spin_lock_irqsave(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) icu1_set(MPIUINTREG, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) raw_spin_unlock_irqrestore(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) EXPORT_SYMBOL(vr41xx_enable_piuint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) void vr41xx_disable_piuint(uint16_t mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct irq_desc *desc = irq_to_desc(PIU_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (current_cpu_type() == CPU_VR4111 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) current_cpu_type() == CPU_VR4121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) raw_spin_lock_irqsave(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) icu1_clear(MPIUINTREG, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) raw_spin_unlock_irqrestore(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) EXPORT_SYMBOL(vr41xx_disable_piuint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) void vr41xx_enable_aiuint(uint16_t mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct irq_desc *desc = irq_to_desc(AIU_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (current_cpu_type() == CPU_VR4111 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) current_cpu_type() == CPU_VR4121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) raw_spin_lock_irqsave(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) icu1_set(MAIUINTREG, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) raw_spin_unlock_irqrestore(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) EXPORT_SYMBOL(vr41xx_enable_aiuint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) void vr41xx_disable_aiuint(uint16_t mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct irq_desc *desc = irq_to_desc(AIU_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (current_cpu_type() == CPU_VR4111 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) current_cpu_type() == CPU_VR4121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) raw_spin_lock_irqsave(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) icu1_clear(MAIUINTREG, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) raw_spin_unlock_irqrestore(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) EXPORT_SYMBOL(vr41xx_disable_aiuint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) void vr41xx_enable_kiuint(uint16_t mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct irq_desc *desc = irq_to_desc(KIU_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (current_cpu_type() == CPU_VR4111 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) current_cpu_type() == CPU_VR4121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) raw_spin_lock_irqsave(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) icu1_set(MKIUINTREG, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) raw_spin_unlock_irqrestore(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) EXPORT_SYMBOL(vr41xx_enable_kiuint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) void vr41xx_disable_kiuint(uint16_t mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct irq_desc *desc = irq_to_desc(KIU_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (current_cpu_type() == CPU_VR4111 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) current_cpu_type() == CPU_VR4121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) raw_spin_lock_irqsave(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) icu1_clear(MKIUINTREG, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) raw_spin_unlock_irqrestore(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) EXPORT_SYMBOL(vr41xx_disable_kiuint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) void vr41xx_enable_macint(uint16_t mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct irq_desc *desc = irq_to_desc(ETHERNET_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) raw_spin_lock_irqsave(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) icu1_set(MMACINTREG, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) raw_spin_unlock_irqrestore(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) EXPORT_SYMBOL(vr41xx_enable_macint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) void vr41xx_disable_macint(uint16_t mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct irq_desc *desc = irq_to_desc(ETHERNET_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) raw_spin_lock_irqsave(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) icu1_clear(MMACINTREG, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) raw_spin_unlock_irqrestore(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) EXPORT_SYMBOL(vr41xx_disable_macint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) void vr41xx_enable_dsiuint(uint16_t mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct irq_desc *desc = irq_to_desc(DSIU_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) raw_spin_lock_irqsave(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) icu1_set(MDSIUINTREG, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) raw_spin_unlock_irqrestore(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) EXPORT_SYMBOL(vr41xx_enable_dsiuint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) void vr41xx_disable_dsiuint(uint16_t mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct irq_desc *desc = irq_to_desc(DSIU_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) raw_spin_lock_irqsave(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) icu1_clear(MDSIUINTREG, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) raw_spin_unlock_irqrestore(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) EXPORT_SYMBOL(vr41xx_disable_dsiuint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) void vr41xx_enable_firint(uint16_t mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct irq_desc *desc = irq_to_desc(FIR_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) raw_spin_lock_irqsave(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) icu2_set(MFIRINTREG, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) raw_spin_unlock_irqrestore(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) EXPORT_SYMBOL(vr41xx_enable_firint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) void vr41xx_disable_firint(uint16_t mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct irq_desc *desc = irq_to_desc(FIR_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) raw_spin_lock_irqsave(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) icu2_clear(MFIRINTREG, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) raw_spin_unlock_irqrestore(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) EXPORT_SYMBOL(vr41xx_disable_firint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) void vr41xx_enable_pciint(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct irq_desc *desc = irq_to_desc(PCI_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (current_cpu_type() == CPU_VR4122 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) current_cpu_type() == CPU_VR4131 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) current_cpu_type() == CPU_VR4133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) raw_spin_lock_irqsave(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) icu2_write(MPCIINTREG, PCIINT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) raw_spin_unlock_irqrestore(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) EXPORT_SYMBOL(vr41xx_enable_pciint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) void vr41xx_disable_pciint(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct irq_desc *desc = irq_to_desc(PCI_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (current_cpu_type() == CPU_VR4122 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) current_cpu_type() == CPU_VR4131 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) current_cpu_type() == CPU_VR4133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) raw_spin_lock_irqsave(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) icu2_write(MPCIINTREG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) raw_spin_unlock_irqrestore(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) EXPORT_SYMBOL(vr41xx_disable_pciint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) void vr41xx_enable_scuint(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct irq_desc *desc = irq_to_desc(SCU_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (current_cpu_type() == CPU_VR4122 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) current_cpu_type() == CPU_VR4131 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) current_cpu_type() == CPU_VR4133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) raw_spin_lock_irqsave(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) icu2_write(MSCUINTREG, SCUINT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) raw_spin_unlock_irqrestore(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) EXPORT_SYMBOL(vr41xx_enable_scuint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) void vr41xx_disable_scuint(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct irq_desc *desc = irq_to_desc(SCU_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (current_cpu_type() == CPU_VR4122 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) current_cpu_type() == CPU_VR4131 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) current_cpu_type() == CPU_VR4133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) raw_spin_lock_irqsave(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) icu2_write(MSCUINTREG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) raw_spin_unlock_irqrestore(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) EXPORT_SYMBOL(vr41xx_disable_scuint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) void vr41xx_enable_csiint(uint16_t mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct irq_desc *desc = irq_to_desc(CSI_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (current_cpu_type() == CPU_VR4122 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) current_cpu_type() == CPU_VR4131 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) current_cpu_type() == CPU_VR4133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) raw_spin_lock_irqsave(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) icu2_set(MCSIINTREG, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) raw_spin_unlock_irqrestore(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) EXPORT_SYMBOL(vr41xx_enable_csiint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) void vr41xx_disable_csiint(uint16_t mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct irq_desc *desc = irq_to_desc(CSI_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (current_cpu_type() == CPU_VR4122 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) current_cpu_type() == CPU_VR4131 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) current_cpu_type() == CPU_VR4133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) raw_spin_lock_irqsave(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) icu2_clear(MCSIINTREG, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) raw_spin_unlock_irqrestore(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) EXPORT_SYMBOL(vr41xx_disable_csiint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) void vr41xx_enable_bcuint(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct irq_desc *desc = irq_to_desc(BCU_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (current_cpu_type() == CPU_VR4122 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) current_cpu_type() == CPU_VR4131 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) current_cpu_type() == CPU_VR4133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) raw_spin_lock_irqsave(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) icu2_write(MBCUINTREG, BCUINTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) raw_spin_unlock_irqrestore(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) EXPORT_SYMBOL(vr41xx_enable_bcuint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) void vr41xx_disable_bcuint(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct irq_desc *desc = irq_to_desc(BCU_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (current_cpu_type() == CPU_VR4122 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) current_cpu_type() == CPU_VR4131 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) current_cpu_type() == CPU_VR4133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) raw_spin_lock_irqsave(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) icu2_write(MBCUINTREG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) raw_spin_unlock_irqrestore(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) EXPORT_SYMBOL(vr41xx_disable_bcuint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static void disable_sysint1_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(d->irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static void enable_sysint1_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(d->irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static struct irq_chip sysint1_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .name = "SYSINT1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .irq_mask = disable_sysint1_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .irq_unmask = enable_sysint1_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static void disable_sysint2_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(d->irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static void enable_sysint2_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(d->irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static struct irq_chip sysint2_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .name = "SYSINT2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .irq_mask = disable_sysint2_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .irq_unmask = enable_sysint2_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static inline int set_sysint1_assign(unsigned int irq, unsigned char assign)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct irq_desc *desc = irq_to_desc(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) uint16_t intassign0, intassign1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) unsigned int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) pin = SYSINT1_IRQ_TO_PIN(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) raw_spin_lock_irq(&desc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) intassign0 = icu1_read(INTASSIGN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) intassign1 = icu1_read(INTASSIGN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) switch (pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) intassign0 &= ~INTASSIGN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) intassign0 |= (uint16_t)assign;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) intassign0 &= ~(INTASSIGN_MASK << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) intassign0 |= (uint16_t)assign << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) intassign0 &= ~(INTASSIGN_MASK << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) intassign0 |= (uint16_t)assign << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) intassign0 &= ~(INTASSIGN_MASK << 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) intassign0 |= (uint16_t)assign << 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) intassign0 &= ~(INTASSIGN_MASK << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) intassign0 |= (uint16_t)assign << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) intassign1 &= ~INTASSIGN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) intassign1 |= (uint16_t)assign;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) case 11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) intassign1 &= ~(INTASSIGN_MASK << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) intassign1 |= (uint16_t)assign << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) case 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) intassign1 &= ~(INTASSIGN_MASK << 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) intassign1 |= (uint16_t)assign << 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) raw_spin_unlock_irq(&desc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) sysint1_assign[pin] = assign;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) icu1_write(INTASSIGN0, intassign0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) icu1_write(INTASSIGN1, intassign1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) raw_spin_unlock_irq(&desc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static inline int set_sysint2_assign(unsigned int irq, unsigned char assign)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct irq_desc *desc = irq_to_desc(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) uint16_t intassign2, intassign3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) unsigned int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) pin = SYSINT2_IRQ_TO_PIN(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) raw_spin_lock_irq(&desc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) intassign2 = icu1_read(INTASSIGN2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) intassign3 = icu1_read(INTASSIGN3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) switch (pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) intassign2 &= ~INTASSIGN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) intassign2 |= (uint16_t)assign;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) intassign2 &= ~(INTASSIGN_MASK << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) intassign2 |= (uint16_t)assign << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) intassign2 &= ~(INTASSIGN_MASK << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) intassign2 |= (uint16_t)assign << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) intassign2 &= ~(INTASSIGN_MASK << 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) intassign2 |= (uint16_t)assign << 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) intassign2 &= ~(INTASSIGN_MASK << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) intassign2 |= (uint16_t)assign << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) intassign3 &= ~INTASSIGN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) intassign3 |= (uint16_t)assign;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) intassign3 &= ~(INTASSIGN_MASK << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) intassign3 |= (uint16_t)assign << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) intassign3 &= ~(INTASSIGN_MASK << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) intassign3 |= (uint16_t)assign << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) case 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) intassign3 &= ~(INTASSIGN_MASK << 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) intassign3 |= (uint16_t)assign << 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) intassign3 &= ~(INTASSIGN_MASK << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) intassign3 |= (uint16_t)assign << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) raw_spin_unlock_irq(&desc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) sysint2_assign[pin] = assign;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) icu1_write(INTASSIGN2, intassign2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) icu1_write(INTASSIGN3, intassign3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) raw_spin_unlock_irq(&desc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) int vr41xx_set_intassign(unsigned int irq, unsigned char intassign)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) int retval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (current_cpu_type() != CPU_VR4133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (intassign > INTASSIGN_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (irq >= SYSINT1_IRQ_BASE && irq <= SYSINT1_IRQ_LAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) retval = set_sysint1_assign(irq, intassign);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) else if (irq >= SYSINT2_IRQ_BASE && irq <= SYSINT2_IRQ_LAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) retval = set_sysint2_assign(irq, intassign);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) EXPORT_SYMBOL(vr41xx_set_intassign);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static int icu_get_irq(unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) uint16_t pend1, pend2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) uint16_t mask1, mask2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) pend1 = icu1_read(SYSINT1REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) mask1 = icu1_read(MSYSINT1REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) pend2 = icu2_read(SYSINT2REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) mask2 = icu2_read(MSYSINT2REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) mask1 &= pend1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) mask2 &= pend2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (mask1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (irq == INT_TO_IRQ(sysint1_assign[i]) && (mask1 & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return SYSINT1_IRQ(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (mask2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (irq == INT_TO_IRQ(sysint2_assign[i]) && (mask2 & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return SYSINT2_IRQ(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) printk(KERN_ERR "spurious ICU interrupt: %04x,%04x\n", pend1, pend2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) atomic_inc(&irq_err_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static int __init vr41xx_icu_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) unsigned long icu1_start, icu2_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) switch (current_cpu_type()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) case CPU_VR4111:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) case CPU_VR4121:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) icu1_start = ICU1_TYPE1_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) icu2_start = ICU2_TYPE1_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) case CPU_VR4122:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) case CPU_VR4131:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) case CPU_VR4133:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) icu1_start = ICU1_TYPE2_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) icu2_start = ICU2_TYPE2_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) printk(KERN_ERR "ICU: Unexpected CPU of NEC VR4100 series\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (request_mem_region(icu1_start, ICU1_SIZE, "ICU") == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (request_mem_region(icu2_start, ICU2_SIZE, "ICU") == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) release_mem_region(icu1_start, ICU1_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) icu1_base = ioremap(icu1_start, ICU1_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (icu1_base == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) release_mem_region(icu1_start, ICU1_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) release_mem_region(icu2_start, ICU2_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) icu2_base = ioremap(icu2_start, ICU2_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (icu2_base == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) iounmap(icu1_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) release_mem_region(icu1_start, ICU1_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) release_mem_region(icu2_start, ICU2_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) icu1_write(MSYSINT1REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) icu1_write(MGIUINTLREG, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) icu2_write(MSYSINT2REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) icu2_write(MGIUINTHREG, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) irq_set_chip_and_handler(i, &sysint1_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) irq_set_chip_and_handler(i, &sysint2_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) cascade_irq(INT0_IRQ, icu_get_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) cascade_irq(INT1_IRQ, icu_get_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) cascade_irq(INT2_IRQ, icu_get_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) cascade_irq(INT3_IRQ, icu_get_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) cascade_irq(INT4_IRQ, icu_get_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) core_initcall(vr41xx_icu_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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