Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  cmu.c, Clock Mask Unit routines for the NEC VR4100 series.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2001-2002  MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *    Author: Yoichi Yuasa <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Copyright (C) 2003-2005  Yoichi Yuasa <yuasa@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Changes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *  MontaVista Software Inc. <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *  - New creation, NEC VR4122 and VR4131 are supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *  - Added support for NEC VR4111 and VR4121.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *  Yoichi Yuasa <yuasa@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *  - Added support for NEC VR4133.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <asm/vr41xx/vr41xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CMU_TYPE1_BASE	0x0b000060UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CMU_TYPE1_SIZE	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CMU_TYPE2_BASE	0x0f000060UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define CMU_TYPE2_SIZE	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CMU_TYPE3_BASE	0x0f000060UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CMU_TYPE3_SIZE	0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CMUCLKMSK	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  #define MSKPIU		0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  #define MSKSIU		0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  #define MSKAIU		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  #define MSKKIU		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  #define MSKFIR		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  #define MSKDSIU	0x0820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  #define MSKCSI		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  #define MSKPCIU	0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  #define MSKSSIU	0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  #define MSKSHSP	0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  #define MSKFFIR	0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  #define MSKSCSI	0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  #define MSKPPCIU	0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define CMUCLKMSK2	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  #define MSKCEU		0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  #define MSKMAC0	0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  #define MSKMAC1	0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static void __iomem *cmu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static uint16_t cmuclkmsk, cmuclkmsk2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static DEFINE_SPINLOCK(cmu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define cmu_read(offset)		readw(cmu_base + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define cmu_write(offset, value)	writew((value), cmu_base + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) void vr41xx_supply_clock(vr41xx_clock_t clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	spin_lock_irq(&cmu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	case PIU_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		cmuclkmsk |= MSKPIU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	case SIU_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		cmuclkmsk |= MSKSIU | MSKSSIU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	case AIU_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		cmuclkmsk |= MSKAIU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	case KIU_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		cmuclkmsk |= MSKKIU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	case FIR_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		cmuclkmsk |= MSKFIR | MSKFFIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	case DSIU_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		if (current_cpu_type() == CPU_VR4111 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		    current_cpu_type() == CPU_VR4121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			cmuclkmsk |= MSKDSIU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			cmuclkmsk |= MSKSIU | MSKDSIU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	case CSI_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		cmuclkmsk |= MSKCSI | MSKSCSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	case PCIU_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		cmuclkmsk |= MSKPCIU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	case HSP_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		cmuclkmsk |= MSKSHSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	case PCI_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		cmuclkmsk |= MSKPPCIU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	case CEU_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		cmuclkmsk2 |= MSKCEU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	case ETHER0_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		cmuclkmsk2 |= MSKMAC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	case ETHER1_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		cmuclkmsk2 |= MSKMAC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (clock == CEU_CLOCK || clock == ETHER0_CLOCK ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	    clock == ETHER1_CLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		cmu_write(CMUCLKMSK2, cmuclkmsk2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		cmu_write(CMUCLKMSK, cmuclkmsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	spin_unlock_irq(&cmu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) EXPORT_SYMBOL_GPL(vr41xx_supply_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void vr41xx_mask_clock(vr41xx_clock_t clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	spin_lock_irq(&cmu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	case PIU_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		cmuclkmsk &= ~MSKPIU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	case SIU_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		if (current_cpu_type() == CPU_VR4111 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		    current_cpu_type() == CPU_VR4121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			cmuclkmsk &= ~(MSKSIU | MSKSSIU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			if (cmuclkmsk & MSKDSIU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 				cmuclkmsk &= ~MSKSSIU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 				cmuclkmsk &= ~(MSKSIU | MSKSSIU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	case AIU_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		cmuclkmsk &= ~MSKAIU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	case KIU_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		cmuclkmsk &= ~MSKKIU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	case FIR_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		cmuclkmsk &= ~(MSKFIR | MSKFFIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	case DSIU_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		if (current_cpu_type() == CPU_VR4111 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		    current_cpu_type() == CPU_VR4121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			cmuclkmsk &= ~MSKDSIU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			if (cmuclkmsk & MSKSSIU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 				cmuclkmsk &= ~MSKDSIU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 				cmuclkmsk &= ~(MSKSIU | MSKDSIU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	case CSI_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		cmuclkmsk &= ~(MSKCSI | MSKSCSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	case PCIU_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		cmuclkmsk &= ~MSKPCIU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	case HSP_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		cmuclkmsk &= ~MSKSHSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	case PCI_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		cmuclkmsk &= ~MSKPPCIU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	case CEU_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		cmuclkmsk2 &= ~MSKCEU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	case ETHER0_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		cmuclkmsk2 &= ~MSKMAC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	case ETHER1_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		cmuclkmsk2 &= ~MSKMAC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (clock == CEU_CLOCK || clock == ETHER0_CLOCK ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	    clock == ETHER1_CLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		cmu_write(CMUCLKMSK2, cmuclkmsk2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		cmu_write(CMUCLKMSK, cmuclkmsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	spin_unlock_irq(&cmu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) EXPORT_SYMBOL_GPL(vr41xx_mask_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int __init vr41xx_cmu_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	unsigned long start, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	switch (current_cpu_type()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	case CPU_VR4111:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	case CPU_VR4121:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		start = CMU_TYPE1_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		size = CMU_TYPE1_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	case CPU_VR4122:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	case CPU_VR4131:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		start = CMU_TYPE2_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		size = CMU_TYPE2_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	case CPU_VR4133:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		start = CMU_TYPE3_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		size = CMU_TYPE3_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		panic("Unexpected CPU of NEC VR4100 series");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (request_mem_region(start, size, "CMU") == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	cmu_base = ioremap(start, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	if (cmu_base == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		release_mem_region(start, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	cmuclkmsk = cmu_read(CMUCLKMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	if (current_cpu_type() == CPU_VR4133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		cmuclkmsk2 = cmu_read(CMUCLKMSK2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	spin_lock_init(&cmu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) core_initcall(vr41xx_cmu_init);