Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Setup pointers to hardware-dependent routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2000-2001 Toshiba Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * terms of the GNU General Public License version 2. This program is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * licensed "as is" without any warranty of any kind, whether express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/mtd/physmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/txx9/generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/txx9/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/txx9/rbtx4938.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <asm/txx9/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <asm/txx9pio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) static void rbtx4938_machine_restart(char *command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	writeb(1, rbtx4938_softresetlock_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	writeb(1, rbtx4938_sfvol_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	writeb(1, rbtx4938_softreset_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	/* fallback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	(*_machine_halt)();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static void __init rbtx4938_pci_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct pci_controller *c = &txx9_primary_pcic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	register_pci_controller(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		txx9_pci_option =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 			(txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 			TXX9_PCI_OPT_CLK_66; /* already configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	/* Reset PCI Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	writeb(0, rbtx4938_pcireset_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	/* Reset PCIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	    TXX9_PCI_OPT_CLK_66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		tx4938_pciclk66_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	/* clear PCIC reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	writeb(1, rbtx4938_pcireset_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	tx4938_report_pciclk();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	    TXX9_PCI_OPT_CLK_AUTO &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	    txx9_pci66_check(c, 0, 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		/* Reset PCI Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		writeb(0, rbtx4938_pcireset_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		/* Reset PCIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		tx4938_pciclk66_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		/* clear PCIC reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		writeb(1, rbtx4938_pcireset_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		/* Reinitialize PCIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		tx4938_report_pciclk();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	if (__raw_readq(&tx4938_ccfgptr->pcfg) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	    (TX4938_PCFG_ETH0_SEL|TX4938_PCFG_ETH1_SEL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		/* Reset PCIC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		/* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		if (!(__raw_readq(&tx4938_ccfgptr->ccfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		      & TX4938_CCFG_PCI1DMD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			tx4938_ccfg_set(TX4938_CCFG_PCI1_66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		/* clear PCIC1 reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		tx4938_report_pci1clk();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		/* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		register_pci_controller(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		tx4927_pcic_setup(tx4938_pcic1ptr, c, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	tx4938_setup_pcierr_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #endif /* CONFIG_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* SPI support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* chip select for SPI devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SEEPROM1_CS	7	/* PIO7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SEEPROM2_CS	0	/* IOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SEEPROM3_CS	1	/* IOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SRTC_CS 2	/* IOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SPI_BUSNO	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int __init rbtx4938_ethaddr_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	unsigned char dat[17];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	unsigned char sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	/* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (spi_eeprom_read(SPI_BUSNO, SEEPROM1_CS, 0, dat, sizeof(dat))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		pr_err("seeprom: read error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		if (strcmp(dat, "MAC") != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			pr_warn("seeprom: bad signature.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		for (i = 0, sum = 0; i < sizeof(dat); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			sum += dat[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		if (sum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			pr_warn("seeprom: bad checksum.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	tx4938_ethaddr_init(&dat[4], &dat[4 + 6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #endif /* CONFIG_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void __init rbtx4938_spi_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	/* set SPI_SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_SPI_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static struct resource rbtx4938_fpga_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void __init rbtx4938_time_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	tx4938_time_init(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void __init rbtx4938_mem_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	unsigned long long pcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (txx9_master_clock == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		txx9_master_clock = 25000000; /* 25MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	tx4938_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	txx9_board_pcibios_setup = tx4927_pcibios_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	set_io_port_base(RBTX4938_ETHER_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	tx4938_sio_init(7372800, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	pr_info("PIOSEL: disabling both ATA and NAND selection\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	txx9_clear64(&tx4938_ccfgptr->pcfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		     TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	pr_info("PIOSEL: enabling NAND selection\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	pr_info("PIOSEL: enabling ATA selection\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_KEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	pr_info("PIOSEL: NAND %s, ATA %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		(pcfg & TX4938_PCFG_NDF_SEL) ? "enabled" : "disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		(pcfg & TX4938_PCFG_ATA_SEL) ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	rbtx4938_spi_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);	/* updated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	/* fixup piosel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	    TX4938_PCFG_ATA_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		       rbtx4938_piosel_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		 TX4938_PCFG_NDF_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		       rbtx4938_piosel_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		writeb(readb(rbtx4938_piosel_addr) & ~(0x08 | 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		       rbtx4938_piosel_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	rbtx4938_fpga_resource.name = "FPGA Registers";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (request_resource(&txx9_ce_res[2], &rbtx4938_fpga_resource))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		pr_err("request resource for fpga failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	_machine_restart = rbtx4938_machine_restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	writeb(0xff, rbtx4938_led_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	pr_info("RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		readb(rbtx4938_fpga_rev_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static void __init rbtx4938_ne_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	struct resource res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			.start	= RBTX4938_RTL_8019_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			.end	= RBTX4938_RTL_8019_BASE + 0x20 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			.flags	= IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			.start	= RBTX4938_RTL_8019_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			.flags	= IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 				  int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	val = readb(rbtx4938_spics_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		val |= 1 << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		val &= ~(1 << offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	writeb(val, rbtx4938_spics_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	mmiowb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int rbtx4938_spi_gpio_dir_out(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 				     unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	rbtx4938_spi_gpio_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static struct gpio_chip rbtx4938_spi_gpio_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	.set = rbtx4938_spi_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	.direction_output = rbtx4938_spi_gpio_dir_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	.label = "RBTX4938-SPICS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	.base = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.ngpio = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int __init rbtx4938_spi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	struct spi_board_info srtc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		.modalias = "rtc-rs5c348",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		.max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		.bus_num = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		.chip_select = 16 + SRTC_CS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		/* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		.mode = SPI_MODE_1 | SPI_CS_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	spi_register_board_info(&srtc_info, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	spi_eeprom_register(SPI_BUSNO, SEEPROM1_CS, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	spi_eeprom_register(SPI_BUSNO, 16 + SEEPROM2_CS, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	spi_eeprom_register(SPI_BUSNO, 16 + SEEPROM3_CS, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	gpio_request(16 + SRTC_CS, "rtc-rs5c348");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	gpio_direction_output(16 + SRTC_CS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	gpio_request(SEEPROM1_CS, "seeprom1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	gpio_direction_output(SEEPROM1_CS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	gpio_request(16 + SEEPROM2_CS, "seeprom2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	gpio_direction_output(16 + SEEPROM2_CS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	gpio_request(16 + SEEPROM3_CS, "seeprom3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	gpio_direction_output(16 + SEEPROM3_CS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	tx4938_spi_init(SPI_BUSNO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static void __init rbtx4938_mtd_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	struct physmap_flash_data pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		.width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	switch (readb(rbtx4938_bdipsw_addr) & 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		/* Boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		txx9_physmap_flash_init(0, 0x1fc00000, 0x400000, &pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		/* System */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		txx9_physmap_flash_init(1, 0x1e000000, 0x1000000, &pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		/* System */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		txx9_physmap_flash_init(0, 0x1f000000, 0x1000000, &pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		/* Boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		txx9_physmap_flash_init(1, 0x1ec00000, 0x400000, &pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		/* Ext */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		txx9_physmap_flash_init(0, 0x1f000000, 0x1000000, &pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		/* System */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		txx9_physmap_flash_init(1, 0x1e000000, 0x1000000, &pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		/* Boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		txx9_physmap_flash_init(2, 0x1dc00000, 0x400000, &pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		/* Boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		txx9_physmap_flash_init(1, 0x1bc00000, 0x400000, &pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		/* System */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		txx9_physmap_flash_init(2, 0x1a000000, 0x1000000, &pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static void __init rbtx4938_arch_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	gpiochip_add_data(&rbtx4938_spi_gpio_chip, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	rbtx4938_pci_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	rbtx4938_spi_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static void __init rbtx4938_device_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	rbtx4938_ethaddr_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	rbtx4938_ne_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	tx4938_wdt_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	rbtx4938_mtd_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	/* TC58DVM82A1FT: tDH=10ns, tWP=tRP=tREADID=35ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	tx4938_ndfmc_init(10, 35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	tx4938_ata_init(RBTX4938_IRQ_IOC_ATA, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	tx4938_dmac_init(0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	tx4938_aclc_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	platform_device_register_simple("txx9aclc-generic", -1, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	tx4938_sramc_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	txx9_iocled_init(RBTX4938_LED_ADDR - IO_BASE, -1, 8, 1, "green", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct txx9_board_vec rbtx4938_vec __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	.system = "Toshiba RBTX4938",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	.prom_init = rbtx4938_prom_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	.mem_setup = rbtx4938_mem_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	.irq_setup = rbtx4938_irq_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	.time_init = rbtx4938_time_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	.device_init = rbtx4938_device_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	.arch_init = rbtx4938_arch_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	.pci_map_irq = rbtx4938_pci_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };