Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Toshiba rbtx4927 specific setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *	   source@mvista.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright 2001-2002 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) 1996, 97, 2001, 04  Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Copyright (C) 2000 RidgeRun, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Author: RidgeRun, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Copyright 2001 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * Author: jsun@mvista.com or jsun@junsun.net
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * Copyright 2002 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * Author: Michael Pruznick, michael_pruznick@mvista.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * Copyright (C) 2000-2001 Toshiba Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * Copyright (C) 2004 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * Author: Manish Lachwani, mlachwani@mvista.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *  This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *  under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *  Free Software Foundation; either version 2 of the License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *  option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  *  You should have received a copy of the GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  *  with this program; if not, write to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  *  675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #include <linux/leds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #include <asm/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #include <asm/txx9pio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #include <asm/txx9/generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #include <asm/txx9/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #include <asm/txx9/rbtx4927.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #include <asm/txx9/tx4938.h>	/* for TX4937 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static void __init tx4927_pci_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct pci_controller *c = &txx9_primary_pcic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	register_pci_controller(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		txx9_pci_option =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			(txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 			TXX9_PCI_OPT_CLK_66; /* already configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	/* Reset PCI Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	writeb(1, rbtx4927_pcireset_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	/* Reset PCIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	    TXX9_PCI_OPT_CLK_66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		tx4927_pciclk66_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	/* clear PCIC reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	writeb(0, rbtx4927_pcireset_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	tx4927_report_pciclk();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	    TXX9_PCI_OPT_CLK_AUTO &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	    txx9_pci66_check(c, 0, 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		/* Reset PCI Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		writeb(1, rbtx4927_pcireset_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		/* Reset PCIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		tx4927_pciclk66_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		/* clear PCIC reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		writeb(0, rbtx4927_pcireset_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		/* Reinitialize PCIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		tx4927_report_pciclk();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	tx4927_setup_pcierr_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void __init tx4937_pci_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct pci_controller *c = &txx9_primary_pcic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	register_pci_controller(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		txx9_pci_option =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			(txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			TXX9_PCI_OPT_CLK_66; /* already configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	/* Reset PCI Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	writeb(1, rbtx4927_pcireset_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	/* Reset PCIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	    TXX9_PCI_OPT_CLK_66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		tx4938_pciclk66_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	/* clear PCIC reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	writeb(0, rbtx4927_pcireset_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	tx4938_report_pciclk();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	    TXX9_PCI_OPT_CLK_AUTO &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	    txx9_pci66_check(c, 0, 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		/* Reset PCI Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		writeb(1, rbtx4927_pcireset_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		/* Reset PCIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		tx4938_pciclk66_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		/* clear PCIC reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		writeb(0, rbtx4927_pcireset_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		/* Reinitialize PCIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		tx4938_report_pciclk();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	tx4938_setup_pcierr_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static inline void tx4927_pci_setup(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static inline void tx4937_pci_setup(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #endif /* CONFIG_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void __init rbtx4927_gpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	/* TX4927-SIO DTR on (PIO[15]) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	gpio_request(15, "sio-dtr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	gpio_direction_output(15, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	tx4927_sio_init(0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static void __init rbtx4927_arch_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	txx9_gpio_init(TX4927_PIO_REG & 0xfffffffffULL, 0, TX4927_NUM_PIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	rbtx4927_gpio_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	tx4927_pci_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static void __init rbtx4937_arch_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	rbtx4927_gpio_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	tx4937_pci_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static void toshiba_rbtx4927_restart(char *command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/* enable the s/w reset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	writeb(1, rbtx4927_softresetlock_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* wait for enable to be seen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	while (!(readb(rbtx4927_softresetlock_addr) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	/* do a s/w reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	writeb(1, rbtx4927_softreset_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	/* fallback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	(*_machine_halt)();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void __init rbtx4927_clock_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static void __init rbtx4937_clock_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static void __init rbtx4927_mem_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (TX4927_REV_PCODE() == 0x4927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		rbtx4927_clock_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		tx4927_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		rbtx4937_clock_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		tx4938_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	_machine_restart = toshiba_rbtx4927_restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	txx9_alloc_pci_controller(&txx9_primary_pcic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 				  RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 				  RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	txx9_board_pcibios_setup = tx4927_pcibios_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static void __init rbtx4927_clock_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	 * For TX4927:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	 * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	 * i.e. S9[3]: ON (83MHz), OFF (100MHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		TX4927_CCFG_PCIDIVMODE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	case TX4927_CCFG_PCIDIVMODE_2_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	case TX4927_CCFG_PCIDIVMODE_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		txx9_cpu_clock = 166666666;	/* 166MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		txx9_cpu_clock = 200000000;	/* 200MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static void __init rbtx4937_clock_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	 * For TX4937:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	 * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	 * PCIDIVMODE[10] is 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	 * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	 * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	 * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	 * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	 * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	 * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		TX4938_CCFG_PCIDIVMODE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	case TX4938_CCFG_PCIDIVMODE_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	case TX4938_CCFG_PCIDIVMODE_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		txx9_cpu_clock = 266666666;	/* 266MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	case TX4938_CCFG_PCIDIVMODE_9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	case TX4938_CCFG_PCIDIVMODE_4_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		txx9_cpu_clock = 300000000;	/* 300MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		txx9_cpu_clock = 333333333;	/* 333MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static void __init rbtx4927_time_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	tx4927_time_init(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static void __init toshiba_rbtx4927_rtc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	struct resource res = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		.start	= RBTX4927_BRAMRTC_BASE - IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		.end	= RBTX4927_BRAMRTC_BASE - IO_BASE + 0x800 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		.flags	= IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	platform_device_register_simple("rtc-ds1742", -1, &res, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static void __init rbtx4927_ne_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	struct resource res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			.start	= RBTX4927_RTL_8019_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			.end	= RBTX4927_RTL_8019_BASE + 0x20 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			.flags	= IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			.start	= RBTX4927_RTL_8019_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			.flags	= IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static void __init rbtx4927_mtd_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	for (i = 0; i < 2; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		tx4927_mtd_init(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static void __init rbtx4927_gpioled_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	static const struct gpio_led leds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		{ .name = "gpioled:green:0", .gpio = 0, .active_low = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		{ .name = "gpioled:green:1", .gpio = 1, .active_low = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	static struct gpio_led_platform_data pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		.num_leds = ARRAY_SIZE(leds),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		.leds = leds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	struct platform_device *pdev = platform_device_alloc("leds-gpio", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	if (!pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	pdev->dev.platform_data = &pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	if (platform_device_add(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		platform_device_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static void __init rbtx4927_device_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	toshiba_rbtx4927_rtc_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	rbtx4927_ne_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	tx4927_wdt_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	rbtx4927_mtd_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (TX4927_REV_PCODE() == 0x4927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		tx4927_dmac_init(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		tx4927_aclc_init(0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		tx4938_dmac_init(0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		tx4938_aclc_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	platform_device_register_simple("txx9aclc-generic", -1, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	txx9_iocled_init(RBTX4927_LED_ADDR - IO_BASE, -1, 3, 1, "green", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	rbtx4927_gpioled_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct txx9_board_vec rbtx4927_vec __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	.system = "Toshiba RBTX4927",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	.prom_init = rbtx4927_prom_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	.mem_setup = rbtx4927_mem_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	.irq_setup = rbtx4927_irq_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	.time_init = rbtx4927_time_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	.device_init = rbtx4927_device_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	.arch_init = rbtx4927_arch_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	.pci_map_irq = rbtx4927_pci_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct txx9_board_vec rbtx4937_vec __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	.system = "Toshiba RBTX4937",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	.prom_init = rbtx4927_prom_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	.mem_setup = rbtx4927_mem_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	.irq_setup = rbtx4927_irq_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	.time_init = rbtx4927_time_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	.device_init = rbtx4927_device_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	.arch_init = rbtx4937_arch_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	.pci_map_irq = rbtx4927_pci_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };