Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  *  This program is free software; you can redistribute  it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  under  the terms of  the GNU General  Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *  Free Software Foundation;  either version 2 of the  License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *  You should have received a copy of the  GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *  with this program; if not, write  to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *  675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * Copyright 2001 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * Author: MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *              ahennessy@mvista.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * Copyright (C) 2000-2001 Toshiba Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <asm/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include <asm/txx9pio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include <asm/txx9/generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include <asm/txx9/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include <asm/txx9/jmr3927.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static void jmr3927_machine_restart(char *command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #if 1	/* Resetting PCI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	(void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR);	/* flush WB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	/* fallback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	(*_machine_halt)();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static void __init jmr3927_time_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	tx3927_time_init(0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define DO_WRITE_THROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static void jmr3927_board_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static void __init jmr3927_mem_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	_machine_restart = jmr3927_machine_restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	/* cache setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		unsigned int conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #ifdef DO_WRITE_THROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		int mips_config_cwfon = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		int mips_config_wbon = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		int mips_config_cwfon = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		int mips_config_wbon = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		conf = read_c0_conf();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		conf &= ~(TX39_CONF_WBON | TX39_CONF_CWFON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		write_c0_conf(conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		write_c0_cache(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	/* initialize board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	jmr3927_board_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	tx3927_sio_init(0, 1 << 1); /* ch1: noCTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void __init jmr3927_pci_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	int extarb = !(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct pci_controller *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	c = txx9_alloc_pci_controller(&txx9_primary_pcic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 				      JMR3927_PCIMEM, JMR3927_PCIMEM_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 				      JMR3927_PCIIO, JMR3927_PCIIO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	register_pci_controller(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (!extarb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		/* Reset PCI Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 				    JMR3927_IOC_RESET_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	tx3927_pcic_setup(c, JMR3927_SDRAM_SIZE, extarb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	tx3927_setup_pcierr_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #endif /* CONFIG_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void __init jmr3927_board_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	txx9_cpu_clock = JMR3927_CORECLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	/* SDRAMC are configured by PROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	/* ROMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	/* Pin selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	tx3927_ccfgptr->pcfg |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		(TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	tx3927_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	/* PIO[15:12] connected to LEDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	__raw_writel(0x0000f000, &tx3927_pioptr->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	jmr3927_pci_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	/* SIO0 DTR on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	jmr3927_led_set(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	pr_info("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		jmr3927_dipsw1(), jmr3927_dipsw2(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		jmr3927_dipsw3(), jmr3927_dipsw4());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* This trick makes rtc-ds1742 driver usable as is. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static unsigned long jmr3927_swizzle_addr_b(unsigned long port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if ((port & 0xffff0000) != JMR3927_IOC_NVRAMB_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		return port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	port = (port & 0xffff0000) | (port & 0x7fff << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	return port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	return port | 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static void __init jmr3927_rtc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	static struct resource __initdata res = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		.start	= JMR3927_IOC_NVRAMB_ADDR - IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		.end	= JMR3927_IOC_NVRAMB_ADDR - IO_BASE + 0x800 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		.flags	= IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	platform_device_register_simple("rtc-ds1742", -1, &res, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static void __init jmr3927_mtd_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	for (i = 0; i < 2; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		tx3927_mtd_init(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void __init jmr3927_device_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	unsigned long iocled_base = JMR3927_IOC_LED_ADDR - IO_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #ifdef __LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	iocled_base |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	__swizzle_addr_b = jmr3927_swizzle_addr_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	jmr3927_rtc_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	tx3927_wdt_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	jmr3927_mtd_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	txx9_iocled_init(iocled_base, -1, 8, 1, "green", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static void __init jmr3927_arch_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	txx9_gpio_init(TX3927_PIO_REG, 0, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	gpio_request(11, "dipsw1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	gpio_request(10, "dipsw2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct txx9_board_vec jmr3927_vec __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.system = "Toshiba JMR_TX3927",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.prom_init = jmr3927_prom_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.mem_setup = jmr3927_mem_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.irq_setup = jmr3927_irq_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	.time_init = jmr3927_time_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.device_init = jmr3927_device_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	.arch_init = jmr3927_arch_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	.pci_map_irq = jmr3927_pci_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };