^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * linux/arch/mips/txx9/pci.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Based on linux/arch/mips/txx9/rbtx4927/setup.c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * linux/arch/mips/txx9/rbtx4938/setup.c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * and RBTX49xx patch from CELF patch archive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright 2001-2005 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/txx9/generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/txx9/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #ifdef CONFIG_TOSHIBA_FPCIB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/i8259.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/txx9/smsc_fdc37m81x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) early_read_config_word(struct pci_controller *hose,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int top_bus, int bus, int devfn, int offset, u16 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct pci_bus fake_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) fake_bus.number = bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) fake_bus.sysdata = hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) fake_bus.ops = hose->pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (bus != top_bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Fake a parent bus structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) fake_bus.parent = &fake_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) fake_bus.parent = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return pci_bus_read_config_word(&fake_bus, devfn, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int __init txx9_pci66_check(struct pci_controller *hose, int top_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int current_bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 pci_devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned short vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int cap66 = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u16 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* It seems SLC90E66 needs some time after PCI reset... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) mdelay(80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) pr_info("PCI: Checking 66MHz capabilities...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (PCI_FUNC(pci_devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (early_read_config_word(hose, top_bus, current_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) pci_devfn, PCI_VENDOR_ID, &vid) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PCIBIOS_SUCCESSFUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (vid == 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* check 66MHz capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (cap66 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) cap66 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (cap66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) early_read_config_word(hose, top_bus, current_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pci_devfn, PCI_STATUS, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (!(stat & PCI_STATUS_66MHZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pr_debug("PCI: %02x:%02x not 66MHz capable.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) current_bus, pci_devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) cap66 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return cap66 > 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static struct resource primary_pci_mem_res[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { .name = "PCI MEM" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { .name = "PCI MMIO" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static struct resource primary_pci_io_res = { .name = "PCI IO" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct pci_controller txx9_primary_pcic = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .mem_resource = &primary_pci_mem_res[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .io_resource = &primary_pci_io_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int txx9_pci_mem_high __initdata = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int txx9_pci_mem_high __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * allocate pci_controller and resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * mem_base, io_base: physical address. 0 for auto assignment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * mem_size and io_size means max size on auto assignment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * pcic must be &txx9_primary_pcic or NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct pci_controller *__init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) txx9_alloc_pci_controller(struct pci_controller *pcic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned long mem_base, unsigned long mem_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned long io_base, unsigned long io_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct pcic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct pci_controller c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct resource r_mem[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct resource r_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) } *new = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int min_size = 0x10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (!pcic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) new = kzalloc(sizeof(*new), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (!new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) new->r_mem[0].name = "PCI mem";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) new->r_mem[1].name = "PCI mmio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) new->r_io.name = "PCI io";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) new->c.mem_resource = new->r_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) new->c.io_resource = &new->r_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) pcic = &new->c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) BUG_ON(pcic != &txx9_primary_pcic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pcic->io_resource->flags = IORESOURCE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * for auto assignment, first search a (big) region for PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * MEM, then search a region for PCI IO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (mem_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) pcic->mem_resource[0].start = mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pcic->mem_resource[0].end = mem_base + mem_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (request_resource(&iomem_resource, &pcic->mem_resource[0]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) goto free_and_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned long min = 0, max = 0x20000000; /* low 512MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (!mem_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* default size for auto assignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (txx9_pci_mem_high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) mem_size = 0x20000000; /* mem:512M(max) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) mem_size = 0x08000000; /* mem:128M(max) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (txx9_pci_mem_high) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) min = 0x20000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) max = 0xe0000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* search free region for PCI MEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) for (; mem_size >= min_size; mem_size /= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (allocate_resource(&iomem_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) &pcic->mem_resource[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) mem_size, min, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) mem_size, NULL, NULL) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (mem_size < min_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) goto free_and_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) pcic->mem_resource[1].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (io_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pcic->mem_resource[1].start = io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) pcic->mem_resource[1].end = io_base + io_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (request_resource(&iomem_resource, &pcic->mem_resource[1]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) goto release_and_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (!io_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* default size for auto assignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) io_size = 0x01000000; /* io:16M(max) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* search free region for PCI IO in low 512MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) for (; io_size >= min_size; io_size /= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (allocate_resource(&iomem_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) &pcic->mem_resource[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) io_size, 0, 0x20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) io_size, NULL, NULL) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (io_size < min_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) goto release_and_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) io_base = pcic->mem_resource[1].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) pcic->mem_resource[0].flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (pcic == &txx9_primary_pcic &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) mips_io_port_base == (unsigned long)-1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* map ioport 0 to PCI I/O space address 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) set_io_port_base(IO_BASE + pcic->mem_resource[1].start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pcic->io_resource->start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pcic->io_offset = 0; /* busaddr == ioaddr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pcic->io_map_base = IO_BASE + pcic->mem_resource[1].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* physaddr to ioaddr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) pcic->io_resource->start =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) io_base - (mips_io_port_base - IO_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pcic->io_offset = io_base - (mips_io_port_base - IO_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pcic->io_map_base = mips_io_port_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pcic->io_resource->end = pcic->io_resource->start + io_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pcic->mem_offset = 0; /* busaddr == physaddr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pr_info("PCI: IO %pR MEM %pR\n", &pcic->mem_resource[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) &pcic->mem_resource[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* register_pci_controller() will request MEM resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) release_resource(&pcic->mem_resource[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return pcic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) release_and_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) release_resource(&pcic->mem_resource[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) free_and_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) kfree(new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) pr_err("PCI: Failed to allocate resources.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) txx9_arch_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PCIBIOS_MIN_IO = 0x8000; /* reseve legacy I/O space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) arch_initcall(txx9_arch_pci_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* IRQ/IDSEL mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int txx9_pci_option =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #ifdef CONFIG_PICMG_PCI_BACKPLANE_DEFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) TXX9_PCI_OPT_PICMG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) TXX9_PCI_OPT_CLK_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) enum txx9_pci_err_action txx9_pci_err_action = TXX9_PCI_ERR_REPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #ifdef CONFIG_TOSHIBA_FPCIB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static irqreturn_t i8259_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int isairq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) isairq = i8259_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (unlikely(isairq <= I8259A_IRQ_BASE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) generic_handle_irq(isairq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int txx9_i8259_irq_setup(int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) init_i8259_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) err = request_irq(irq, &i8259_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) "cascade(i8259)", (void *)(long)irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pr_info("PCI-ISA bridge PIC (irq %d)\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static void __ref quirk_slc90e66_bridge(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int irq; /* PCI/ISA Bridge interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u8 reg_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 reg_b0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u8 reg_e1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) irq = pcibios_map_irq(dev, PCI_SLOT(dev->devfn), 1); /* INTA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (!irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) txx9_i8259_irq_setup(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pci_read_config_byte(dev, 0x64, ®_64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) pci_read_config_dword(dev, 0xb0, ®_b0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pci_read_config_byte(dev, 0xe1, ®_e1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* serial irq control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) reg_64 = 0xd0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* serial irq pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) reg_b0 |= 0x00010000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* ide irq on isa14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) reg_e1 &= 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) reg_e1 |= 0x0d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) pci_write_config_byte(dev, 0x64, reg_64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) pci_write_config_dword(dev, 0xb0, reg_b0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) pci_write_config_byte(dev, 0xe1, reg_e1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) smsc_fdc37m81x_init(0x3f0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) smsc_fdc37m81x_config_beg();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) SMSC_FDC37M81X_KBD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) smsc_fdc37m81x_config_end();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static void quirk_slc90e66_ide(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned char dat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int regs[2] = {0x41, 0x43};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* SMSC SLC90E66 IDE uses irq 14, 15 (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) pr_info("PCI: %s: IRQ %02x", pci_name(dev), dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* enable SMSC SLC90E66 IDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) for (i = 0; i < ARRAY_SIZE(regs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pci_read_config_byte(dev, regs[i], &dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) pci_write_config_byte(dev, regs[i], dat | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) pci_read_config_byte(dev, regs[i], &dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) pr_cont(" IDETIM%d %02x", i, dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) pci_read_config_byte(dev, 0x5c, &dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * This line of code is intended to provide the user with a work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * around solution to the anomalies cited in SMSC's anomaly sheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dat |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) pci_write_config_byte(dev, 0x5c, dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) pci_read_config_byte(dev, 0x5c, &dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) pr_cont(" REG5C %02x\n", dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #endif /* CONFIG_TOSHIBA_FPCIB0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static void tc35815_fixup(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* This device may have PM registers but not they are not supported. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (dev->pm_cap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_info(&dev->dev, "PM disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dev->pm_cap = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static void final_fixup(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) unsigned char bist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* Do build-in self test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (pci_read_config_byte(dev, PCI_BIST, &bist) == PCIBIOS_SUCCESSFUL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) (bist & PCI_BIST_CAPABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pci_set_power_state(dev, PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) pr_info("PCI: %s BIST...", pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) timeout = jiffies + HZ * 2; /* timeout after 2 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) pci_read_config_byte(dev, PCI_BIST, &bist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) } while (bist & PCI_BIST_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (bist & (PCI_BIST_CODE_MASK | PCI_BIST_START))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) pr_cont("failed. (0x%x)\n", bist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) pr_cont("OK.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #ifdef CONFIG_TOSHIBA_FPCIB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) quirk_slc90e66_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) quirk_slc90e66_ide);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) quirk_slc90e66_ide);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) PCI_DEVICE_ID_TOSHIBA_TC35815_NWU, tc35815_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939, tc35815_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int pcibios_plat_dev_init(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int (*txx9_pci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return txx9_pci_map_irq(dev, slot, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) char * (*txx9_board_pcibios_setup)(char *str) __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) char *__init txx9_pcibios_setup(char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (txx9_board_pcibios_setup && !txx9_board_pcibios_setup(str))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (!strcmp(str, "picmg")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* PICMG compliant backplane (TOSHIBA JMB-PICMG-ATX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) (5V or 3.3V), JMB-PICMG-L2 (5V only), etc.) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) txx9_pci_option |= TXX9_PCI_OPT_PICMG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) } else if (!strcmp(str, "nopicmg")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* non-PICMG compliant backplane (TOSHIBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) RBHBK4100,RBHBK4200, Interface PCM-PCM05, etc.) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) txx9_pci_option &= ~TXX9_PCI_OPT_PICMG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) } else if (!strncmp(str, "clk=", 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) char *val = str + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) txx9_pci_option &= ~TXX9_PCI_OPT_CLK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (strcmp(val, "33") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) txx9_pci_option |= TXX9_PCI_OPT_CLK_33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) else if (strcmp(val, "66") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) txx9_pci_option |= TXX9_PCI_OPT_CLK_66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) else /* "auto" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) txx9_pci_option |= TXX9_PCI_OPT_CLK_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) } else if (!strncmp(str, "err=", 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (!strcmp(str + 4, "panic"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) txx9_pci_err_action = TXX9_PCI_ERR_PANIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) else if (!strcmp(str + 4, "ignore"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) txx9_pci_err_action = TXX9_PCI_ERR_IGNORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) txx9_pci_map_irq = txx9_board_vec->pci_map_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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