Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * PCI Tower specific code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/serial_8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/sni.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/irq_cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define PORT(_base,_irq)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	{						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 		.iobase		= _base,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		.irq		= _irq,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		.uartclk	= 1843200,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		.iotype		= UPIO_PORT,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		.flags		= UPF_BOOT_AUTOCONF,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static struct plat_serial8250_port pcit_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	PORT(0x3f8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	PORT(0x2f8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static struct platform_device pcit_serial8250_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	.name			= "serial8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	.id			= PLAT8250_DEV_PLATFORM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	.dev			= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		.platform_data	= pcit_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static struct plat_serial8250_port pcit_cplus_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	PORT(0x3f8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	PORT(0x2f8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	PORT(0x3e8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	PORT(0x2e8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static struct platform_device pcit_cplus_serial8250_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	.name			= "serial8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	.id			= PLAT8250_DEV_PLATFORM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.dev			= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		.platform_data	= pcit_cplus_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static struct resource pcit_cmos_rsrc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		.start = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		.end   = 0x71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		.flags = IORESOURCE_IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		.start = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		.end   = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		.flags = IORESOURCE_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static struct platform_device pcit_cmos_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	.name		= "rtc_cmos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	.num_resources	= ARRAY_SIZE(pcit_cmos_rsrc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	.resource	= pcit_cmos_rsrc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static struct platform_device pcit_pcspeaker_pdev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	.name		= "pcspkr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	.id		= -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static struct resource sni_io_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.start	= 0x00000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.end	= 0x03bfffffUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.name	= "PCIT IO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.flags	= IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static struct resource pcit_io_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		.start	= 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		.end	= 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		.name	= "dma1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		.flags	= IORESOURCE_BUSY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		.start	=  0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		.end	= 0x5f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		.name	= "timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		.flags	= IORESOURCE_BUSY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		.start	=  0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		.end	= 0x6f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		.name	= "keyboard",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		.flags	= IORESOURCE_BUSY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		.start	=  0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		.end	= 0x8f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		.name	= "dma page reg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		.flags	= IORESOURCE_BUSY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		.start	=  0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		.end	= 0xdf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		.name	= "dma2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		.flags	= IORESOURCE_BUSY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		.start	=  0xcf8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		.end	= 0xcfb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		.name	= "PCI config addr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		.flags	= IORESOURCE_BUSY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		.start	=  0xcfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		.end	= 0xcff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		.name	= "PCI config data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		.flags	= IORESOURCE_BUSY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void __init sni_pcit_resource_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	/* request I/O space for devices used on all i[345]86 PCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	for (i = 0; i < ARRAY_SIZE(pcit_io_resources); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		request_resource(&sni_io_resource, pcit_io_resources + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) extern struct pci_ops sni_pcit_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static struct resource sni_mem_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.start	= 0x18000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.end	= 0x1fbfffffUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.name	= "PCIT PCI MEM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.flags	= IORESOURCE_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct pci_controller sni_pcit_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.pci_ops	= &sni_pcit_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.mem_resource	= &sni_mem_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.mem_offset	= 0x00000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.io_resource	= &sni_io_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.io_offset	= 0x00000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.io_map_base	= SNI_PORT_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #endif /* CONFIG_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void enable_pcit_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	*(volatile u32 *)SNI_PCIT_INT_REG |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) void disable_pcit_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	*(volatile u32 *)SNI_PCIT_INT_REG &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static struct irq_chip pcit_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.name = "PCIT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.irq_mask = disable_pcit_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.irq_unmask = enable_pcit_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void pcit_hwint1(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	u32 pending = *(volatile u32 *)SNI_PCIT_INT_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	clear_c0_status(IE_IRQ1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	irq = ffs((pending >> 16) & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (likely(irq > 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		do_IRQ(irq + SNI_PCIT_INT_START - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	set_c0_status(IE_IRQ1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static void pcit_hwint0(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	u32 pending = *(volatile u32 *)SNI_PCIT_INT_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	clear_c0_status(IE_IRQ0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	irq = ffs((pending >> 16) & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (likely(irq > 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		do_IRQ(irq + SNI_PCIT_INT_START - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	set_c0_status(IE_IRQ0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void sni_pcit_hwint(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	u32 pending = read_c0_cause() & read_c0_status();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (pending & C_IRQ1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		pcit_hwint1();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	else if (pending & C_IRQ2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		do_IRQ(MIPS_CPU_IRQ_BASE + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	else if (pending & C_IRQ3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		do_IRQ(MIPS_CPU_IRQ_BASE + 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	else if (pending & C_IRQ5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		do_IRQ(MIPS_CPU_IRQ_BASE + 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void sni_pcit_hwint_cplus(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	u32 pending = read_c0_cause() & read_c0_status();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (pending & C_IRQ0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		pcit_hwint0();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	else if (pending & C_IRQ1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		do_IRQ(MIPS_CPU_IRQ_BASE + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	else if (pending & C_IRQ2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		do_IRQ(MIPS_CPU_IRQ_BASE + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	else if (pending & C_IRQ3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		do_IRQ(MIPS_CPU_IRQ_BASE + 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	else if (pending & C_IRQ5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		do_IRQ(MIPS_CPU_IRQ_BASE + 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) void __init sni_pcit_irq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	mips_cpu_irq_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	*(volatile u32 *)SNI_PCIT_INT_REG = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	sni_hwint = sni_pcit_hwint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	change_c0_status(ST0_IM, IE_IRQ1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (request_irq(SNI_PCIT_INT_START + 6, sni_isa_irq_handler, 0, "ISA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		pr_err("Failed to register ISA interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) void __init sni_pcit_cplus_irq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	mips_cpu_irq_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	*(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	sni_hwint = sni_pcit_hwint_cplus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	change_c0_status(ST0_IM, IE_IRQ0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (request_irq(MIPS_CPU_IRQ_BASE + 3, sni_isa_irq_handler, 0, "ISA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		pr_err("Failed to register ISA interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) void __init sni_pcit_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	ioport_resource.end = sni_io_resource.end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	PCIBIOS_MIN_IO = 0x9000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	register_pci_controller(&sni_pcit_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	sni_pcit_resource_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int __init snirm_pcit_setup_devinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	switch (sni_brd_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	case SNI_BRD_PCI_TOWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		platform_device_register(&pcit_serial8250_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		platform_device_register(&pcit_cmos_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		platform_device_register(&pcit_pcspeaker_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	case SNI_BRD_PCI_TOWER_CPLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		platform_device_register(&pcit_cplus_serial8250_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		platform_device_register(&pcit_cmos_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		platform_device_register(&pcit_pcspeaker_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) device_initcall(snirm_pcit_setup_devinit);