Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * A20R specific code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/serial_8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/sni.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define PORT(_base,_irq)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	{						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 		.iobase		= _base,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 		.irq		= _irq,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 		.uartclk	= 1843200,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		.iotype		= UPIO_PORT,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		.flags		= UPF_BOOT_AUTOCONF,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static struct plat_serial8250_port a20r_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	PORT(0x3f8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	PORT(0x2f8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static struct platform_device a20r_serial8250_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	.name			= "serial8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	.id			= PLAT8250_DEV_PLATFORM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	.dev			= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		.platform_data	= a20r_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static struct resource a20r_ds1216_rsrc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		.start = 0x1c081ffc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		.end   = 0x1c081fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		.flags = IORESOURCE_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static struct platform_device a20r_ds1216_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	.name		= "rtc-ds1216",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	.num_resources	= ARRAY_SIZE(a20r_ds1216_rsrc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	.resource	= a20r_ds1216_rsrc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static struct resource snirm_82596_rsrc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		.start = 0x18000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		.end   = 0x18000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		.flags = IORESOURCE_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		.start = 0x18010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		.end   = 0x18010004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		.flags = IORESOURCE_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		.start = 0x1ff00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		.end   = 0x1ff00020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		.flags = IORESOURCE_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		.start = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		.end   = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		.flags = IORESOURCE_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		.flags = 0x01		     /* 16bit mpu port access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static struct platform_device snirm_82596_pdev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	.name		= "snirm_82596",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.num_resources	= ARRAY_SIZE(snirm_82596_rsrc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.resource	= snirm_82596_rsrc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static struct resource snirm_53c710_rsrc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		.start = 0x19000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		.end   = 0x190fffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		.flags = IORESOURCE_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		.start = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		.end   = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		.flags = IORESOURCE_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static struct platform_device snirm_53c710_pdev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.name		= "snirm_53c710",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.num_resources	= ARRAY_SIZE(snirm_53c710_rsrc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.resource	= snirm_53c710_rsrc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static struct resource sc26xx_rsrc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		.start = 0x1c070000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		.end   = 0x1c0700ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		.flags = IORESOURCE_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		.start = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		.end   = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		.flags = IORESOURCE_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #include <linux/platform_data/serial-sccnxp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct sccnxp_pdata sccnxp_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.reg_shift	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.mctrl_cfg[0]	= MCTRL_SIG(DTR_OP, LINE_OP7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			  MCTRL_SIG(RTS_OP, LINE_OP3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			  MCTRL_SIG(DSR_IP, LINE_IP5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			  MCTRL_SIG(DCD_IP, LINE_IP6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.mctrl_cfg[1]	= MCTRL_SIG(DTR_OP, LINE_OP2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			  MCTRL_SIG(RTS_OP, LINE_OP1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			  MCTRL_SIG(DSR_IP, LINE_IP0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			  MCTRL_SIG(CTS_IP, LINE_IP1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			  MCTRL_SIG(DCD_IP, LINE_IP2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			  MCTRL_SIG(RNG_IP, LINE_IP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static struct platform_device sc26xx_pdev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.name		= "sc2681",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.resource	= sc26xx_rsrc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.num_resources	= ARRAY_SIZE(sc26xx_rsrc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.dev	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		.platform_data	= &sccnxp_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  * Trigger chipset to update CPU's CAUSE IP field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static u32 a20r_update_cause_ip(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	u32 status = read_c0_status();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	write_c0_status(status | 0x00010000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	"	.set	push			\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	"	.set	noat			\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	"	.set	noreorder		\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	"	lw	$1, 0(%0)		\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	"	sb	$0, 0(%1)		\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	"	sync				\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	"	lb	%1, 0(%1)		\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	"	b	1f			\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	"	ori	%1, $1, 2		\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	"	.align	8			\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	"1:					\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	"	nop				\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	"	sw	%1, 0(%0)		\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	"	sync				\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	"	li	%1, 0x20		\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	"2:					\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	"	nop				\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	"	bnez	%1,2b			\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	"	addiu	%1, -1			\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	"	sw	$1, 0(%0)		\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	"	sync				\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		".set	pop			\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	: "Jr" (PCIMT_UCONF), "Jr" (0xbc000000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	write_c0_status(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static inline void unmask_a20r_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	set_c0_status(0x100 << (d->irq - SNI_A20R_IRQ_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	irq_enable_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static inline void mask_a20r_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	clear_c0_status(0x100 << (d->irq - SNI_A20R_IRQ_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	irq_disable_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct irq_chip a20r_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.name		= "A20R",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.irq_mask	= mask_a20r_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.irq_unmask	= unmask_a20r_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  * hwint 0 receive all interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void a20r_hwint(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	u32 cause, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	clear_c0_status(IE_IRQ0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	status = a20r_update_cause_ip();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	cause = read_c0_cause();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	irq = ffs(((cause & status) >> 8) & 0xf8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (likely(irq > 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		do_IRQ(SNI_A20R_IRQ_BASE + irq - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	a20r_update_cause_ip();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	set_c0_status(IE_IRQ0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) void __init sni_a20r_irq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	for (i = SNI_A20R_IRQ_BASE + 2 ; i < SNI_A20R_IRQ_BASE + 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		irq_set_chip_and_handler(i, &a20r_irq_type, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	sni_hwint = a20r_hwint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	change_c0_status(ST0_IM, IE_IRQ0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	if (request_irq(SNI_A20R_IRQ_BASE + 3, sni_isa_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			IRQF_SHARED, "ISA", sni_isa_irq_handler))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		pr_err("Failed to register ISA interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) void sni_a20r_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	/* FIXME, remove if not needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int __init snirm_a20r_setup_devinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	switch (sni_brd_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	case SNI_BRD_TOWER_OASIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	case SNI_BRD_MINITOWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		platform_device_register(&snirm_82596_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		platform_device_register(&snirm_53c710_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		platform_device_register(&sc26xx_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		platform_device_register(&a20r_serial8250_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		platform_device_register(&a20r_ds1216_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		sni_eisa_root_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) device_initcall(snirm_a20r_setup_devinit);