^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel_stat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/sched/task_stack.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/fw/cfe/cfe_api.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/sibyte/sb1250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/sibyte/sb1250_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/sibyte/sb1250_int.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static void *mailbox_set_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static void *mailbox_clear_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static void *mailbox_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * SMP init and finish on secondary CPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void sb1250_smp_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) STATUSF_IP1 | STATUSF_IP0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Set interrupt mask, but don't enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) change_c0_status(ST0_IM, imask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * These are routines for dealing with the sb1250 smp capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * independent of board/firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Simple enough; everything is set up, so just poke the appropriate mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * register, and we should be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static void sb1250_send_ipi_single(int cpu, unsigned int action)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) __raw_writeq((((u64)action) << 48), mailbox_set_regs[cpu]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static inline void sb1250_send_ipi_mask(const struct cpumask *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int action)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) for_each_cpu(i, mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) sb1250_send_ipi_single(i, action);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Code to run on secondary just after probing the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void sb1250_init_secondary(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) extern void sb1250_smp_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) sb1250_smp_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Do any tidying up before marking online and running the idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void sb1250_smp_finish(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) extern void sb1250_clockevent_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) sb1250_clockevent_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) local_irq_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Setup the PC, SP, and GP of a secondary processor and start it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * running!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int sb1250_boot_secondary(int cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) __KSTK_TOS(idle),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) (unsigned long)task_thread_info(idle), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (retval != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Use CFE to find out how many CPUs are available, setting up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * cpu_possible_mask and the logical/physical mappings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * XXXKW will the boot CPU ever not be physical 0?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Common setup before any secondaries are started
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void __init sb1250_smp_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int i, num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) init_cpu_possible(cpumask_of(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) __cpu_number_map[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) __cpu_logical_map[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) for (i = 1, num = 0; i < NR_CPUS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (cfe_cpu_stop(i) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) set_cpu_possible(i, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) __cpu_number_map[i] = ++num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) __cpu_logical_map[num] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void __init sb1250_prepare_cpus(unsigned int max_cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) const struct plat_smp_ops sb_smp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .send_ipi_single = sb1250_send_ipi_single,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .send_ipi_mask = sb1250_send_ipi_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .init_secondary = sb1250_init_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .smp_finish = sb1250_smp_finish,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .boot_secondary = sb1250_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .smp_setup = sb1250_smp_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .prepare_cpus = sb1250_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) void sb1250_mailbox_interrupt(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int irq = K_INT_MBOX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned int action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) kstat_incr_irq_this_cpu(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Load the mailbox register to figure out what we're supposed to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) action = (____raw_readq(mailbox_regs[cpu]) >> 48) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Clear the mailbox to clear the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ____raw_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (action & SMP_RESCHEDULE_YOURSELF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) scheduler_ipi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (action & SMP_CALL_FUNCTION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) irq_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) generic_smp_call_function_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) irq_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags