^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/sibyte/sb1250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/sibyte/sb1250_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/sibyte/sb1250_scd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) unsigned int sb1_pass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) unsigned int soc_pass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) unsigned int soc_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) EXPORT_SYMBOL(soc_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned int periph_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) EXPORT_SYMBOL_GPL(periph_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsigned int zbbus_mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) EXPORT_SYMBOL(zbbus_mhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static char *soc_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static char *pass_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static unsigned int war_pass; /* XXXKW don't overload PASS defines? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int __init setup_bcm1250(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) switch (soc_pass) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) case K_SYS_REVISION_BCM1250_PASS1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) periph_rev = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) pass_str = "Pass 1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) case K_SYS_REVISION_BCM1250_A10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) periph_rev = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) pass_str = "A8/A10";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* XXXKW different war_pass? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) war_pass = K_SYS_REVISION_BCM1250_PASS2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) case K_SYS_REVISION_BCM1250_PASS2_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) periph_rev = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) pass_str = "B1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) case K_SYS_REVISION_BCM1250_B2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) periph_rev = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) pass_str = "B2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) war_pass = K_SYS_REVISION_BCM1250_PASS2_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) case K_SYS_REVISION_BCM1250_PASS3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) periph_rev = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) pass_str = "C0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) case K_SYS_REVISION_BCM1250_C1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) periph_rev = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) pass_str = "C1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (soc_pass < K_SYS_REVISION_BCM1250_PASS2_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) periph_rev = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) pass_str = "A0-A6";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) war_pass = K_SYS_REVISION_BCM1250_PASS2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) printk("Unknown BCM1250 rev %x\n", soc_pass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int sb1250_m3_workaround_needed(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) switch (soc_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) case K_SYS_SOC_TYPE_BCM1250:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) case K_SYS_SOC_TYPE_BCM1250_ALT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) case K_SYS_SOC_TYPE_BCM1250_ALT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) case K_SYS_SOC_TYPE_BCM1125:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) case K_SYS_SOC_TYPE_BCM1125H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return soc_pass < K_SYS_REVISION_BCM1250_C0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static int __init setup_bcm112x(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) switch (soc_pass) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Early build didn't have revid set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) periph_rev = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) pass_str = "A1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) war_pass = K_SYS_REVISION_BCM112x_A1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) case K_SYS_REVISION_BCM112x_A1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) periph_rev = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pass_str = "A1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) case K_SYS_REVISION_BCM112x_A2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) periph_rev = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pass_str = "A2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) case K_SYS_REVISION_BCM112x_A3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) periph_rev = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) pass_str = "A3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) case K_SYS_REVISION_BCM112x_A4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) periph_rev = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) pass_str = "A4";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) case K_SYS_REVISION_BCM112x_B0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) periph_rev = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) pass_str = "B0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) printk("Unknown %s rev %x\n", soc_str, soc_pass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Setup code likely to be common to all SiByte platforms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int __init sys_rev_decode(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) war_pass = soc_pass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) switch (soc_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) case K_SYS_SOC_TYPE_BCM1250:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case K_SYS_SOC_TYPE_BCM1250_ALT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) case K_SYS_SOC_TYPE_BCM1250_ALT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) soc_str = "BCM1250";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ret = setup_bcm1250();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case K_SYS_SOC_TYPE_BCM1120:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) soc_str = "BCM1120";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = setup_bcm112x();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) case K_SYS_SOC_TYPE_BCM1125:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) soc_str = "BCM1125";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ret = setup_bcm112x();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) case K_SYS_SOC_TYPE_BCM1125H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) soc_str = "BCM1125H";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret = setup_bcm112x();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) printk("Unknown SOC type %x\n", soc_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) void __init sb1250_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) uint64_t sys_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int plldiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int bad_config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) sb1_pass = read_c0_prid() & PRID_REV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) soc_type = SYS_SOC_TYPE(sys_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) soc_pass = G_SYS_REVISION(sys_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (sys_rev_decode()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) printk("Restart after failure to identify SiByte chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) machine_restart(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) plldiv = G_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) zbbus_mhz = ((plldiv >> 1) * 50) + ((plldiv & 1) * 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) printk("Broadcom SiByte %s %s @ %d MHz (SB1 rev %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) soc_str, pass_str, zbbus_mhz * 2, sb1_pass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) printk("Board type: %s\n", get_system_type());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) switch (war_pass) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) case K_SYS_REVISION_BCM1250_PASS1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) printk("@@@@ This is a BCM1250 A0-A2 (Pass 1) board, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) "and the kernel doesn't have the proper "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) "workarounds compiled in. @@@@\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) bad_config = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) case K_SYS_REVISION_BCM1250_PASS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Pass 2 - easiest as default for now - so many numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #if !defined(CONFIG_SB1_PASS_2_WORKAROUNDS) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) !defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) printk("@@@@ This is a BCM1250 A3-A10 board, and the "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "kernel doesn't have the proper workarounds "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "compiled in. @@@@\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) bad_config = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #ifdef CONFIG_CPU_HAS_PREFETCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) printk("@@@@ Prefetches may be enabled in this kernel, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "but are buggy on this board. @@@@\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) bad_config = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) case K_SYS_REVISION_BCM1250_PASS2_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #ifndef CONFIG_SB1_PASS_2_WORKAROUNDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) printk("@@@@ This is a BCM1250 B1/B2. board, and the "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "kernel doesn't have the proper workarounds "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "compiled in. @@@@\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) bad_config = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #if defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) !defined(CONFIG_CPU_HAS_PREFETCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) printk("@@@@ This is a BCM1250 B1/B2, but the kernel is "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) "conservatively configured for an 'A' stepping. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "@@@@\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (bad_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) printk("Invalid configuration for this chip.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) machine_restart(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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