^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel_stat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/sibyte/sb1250_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/sibyte/sb1250_int.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/sibyte/sb1250_uart.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/sibyte/sb1250_scd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/sibyte/sb1250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * These are the routines that handle all the low level interrupt stuff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Actions handled here are: initialization of the interrupt map, requesting of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * interrupt lines by handlers, dispatching if interrupts to handlers, probing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * for interrupt lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifdef CONFIG_SIBYTE_HAS_LDT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) extern unsigned long ldt_eoi_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Store the CPU id (not the logical number) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int sb1250_irq_owner[SB1250_NR_IRQS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static DEFINE_RAW_SPINLOCK(sb1250_imr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) void sb1250_mask_irq(int cpu, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u64 cur_ints;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) R_IMR_INTERRUPT_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) cur_ints |= (((u64) 1) << irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) R_IMR_INTERRUPT_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) void sb1250_unmask_irq(int cpu, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u64 cur_ints;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) R_IMR_INTERRUPT_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) cur_ints &= ~(((u64) 1) << irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) R_IMR_INTERRUPT_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int sb1250_set_affinity(struct irq_data *d, const struct cpumask *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int i = 0, old_cpu, cpu, int_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u64 cur_ints;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) i = cpumask_first_and(mask, cpu_online_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Convert logical CPU to physical CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) cpu = cpu_logical_map(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Protect against other affinity changers and IMR manipulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Swizzle each CPU's IMR (but leave the IP selection alone) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) old_cpu = sb1250_irq_owner[irq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) R_IMR_INTERRUPT_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int_on = !(cur_ints & (((u64) 1) << irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (int_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* If it was on, mask it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) cur_ints |= (((u64) 1) << irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) R_IMR_INTERRUPT_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) sb1250_irq_owner[irq] = cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (int_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* unmask for the new CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) R_IMR_INTERRUPT_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) cur_ints &= ~(((u64) 1) << irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) R_IMR_INTERRUPT_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void disable_sb1250_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) sb1250_mask_irq(sb1250_irq_owner[irq], irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void enable_sb1250_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void ack_sb1250_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #ifdef CONFIG_SIBYTE_HAS_LDT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u64 pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * If the interrupt was an HT interrupt, now is the time to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * clear it. NOTE: we assume the HT bridge was set up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * deliver the interrupts to all CPUs (which makes affinity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * changing easier for us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) R_IMR_LDT_INTERRUPT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pending &= ((u64)1 << (irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) for (i=0; i<NR_CPUS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) cpu = cpu_logical_map(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) cpu = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * Clear for all CPUs so an affinity switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * doesn't find an old status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) __raw_writeq(pending,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) IOADDR(A_IMR_REGISTER(cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) R_IMR_LDT_INTERRUPT_CLR)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * Generate EOI. For Pass 1 parts, EOI is a nop. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Pass 2, the LDT world may be edge-triggered, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * this EOI shouldn't hurt. If they are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * level-sensitive, the EOI is required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) sb1250_mask_irq(sb1250_irq_owner[irq], irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static struct irq_chip sb1250_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .name = "SB1250-IMR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .irq_mask_ack = ack_sb1250_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .irq_unmask = enable_sb1250_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .irq_mask = disable_sb1250_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .irq_set_affinity = sb1250_set_affinity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) void __init init_sb1250_irqs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) for (i = 0; i < SB1250_NR_IRQS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) irq_set_chip_and_handler(i, &sb1250_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) sb1250_irq_owner[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * arch_init_irq is called early in the boot sequence from init/main.c via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * init_IRQ. It is responsible for setting up the interrupt mapper and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * installing the handler that will be responsible for dispatching interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * to the "right" place.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * For now, map all interrupts to IP[2]. We could save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * some cycles by parceling out system interrupts to different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * IP lines, but keep it simple for bringup. We'll also direct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * all interrupts to a single CPU; we should probably route
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * PCI and LDT to one cpu and everything else to the other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * to balance the load a bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * On the second cpu, everything is set to IP5, which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * ignored, EXCEPT the mailbox interrupt. That one is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * set to IP[2] so it is handled. This is needed so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * can do cross-cpu function calls, as required by SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IMR_IP2_VAL K_INT_MAP_I0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define IMR_IP3_VAL K_INT_MAP_I1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IMR_IP4_VAL K_INT_MAP_I2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define IMR_IP5_VAL K_INT_MAP_I3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define IMR_IP6_VAL K_INT_MAP_I4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) void __init arch_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) STATUSF_IP1 | STATUSF_IP0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Default everything to IP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) __raw_writeq(IMR_IP2_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) IOADDR(A_IMR_REGISTER(0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) R_IMR_INTERRUPT_MAP_BASE) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) (i << 3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) __raw_writeq(IMR_IP2_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) IOADDR(A_IMR_REGISTER(1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) R_IMR_INTERRUPT_MAP_BASE) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) (i << 3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) init_sb1250_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * Map the high 16 bits of the mailbox registers to IP[3], for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * inter-cpu messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Was I1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) __raw_writeq(IMR_IP3_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) (K_INT_MBOX_0 << 3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) __raw_writeq(IMR_IP3_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) (K_INT_MBOX_0 << 3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Clear the mailboxes. The firmware may leave them dirty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) __raw_writeq(0xffffffffffffffffULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) __raw_writeq(0xffffffffffffffffULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Mask everything except the mailbox registers for both cpus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * Note that the timer interrupts are also mapped, but this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * done in sb1250_time_init(). Also, the profiling driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * does its own management of IP7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Enable necessary IPs, disable the rest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) change_c0_status(ST0_IM, imask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) extern void sb1250_mailbox_interrupt(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static inline void dispatch_ip2(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned long long mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * Default...we've hit an IP[2] interrupt, which means we've got to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * check the 1250 interrupt registers to figure out what to do. Need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * to detect which CPU we're on, now that smp_affinity is supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) R_IMR_INTERRUPT_STATUS_BASE)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) do_IRQ(fls64(mask) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) asmlinkage void plat_irq_dispatch(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned int pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * What a pain. We have to be really careful saving the upper 32 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * of any * register across function calls if we don't want them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * trashed--since were running in -o32, the calling routing never saves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * the full 64 bits of a register across a function call. Being the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * interrupt handler, we're guaranteed that interrupts are disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * during this code so we don't have to worry about random interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * blasting the high 32 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) pending = read_c0_cause() & read_c0_status() & ST0_IM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) do_IRQ(MIPS_CPU_IRQ_BASE + 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) else if (pending & CAUSEF_IP4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) do_IRQ(K_INT_TIMER_0 + cpu); /* sb1250_timer_interrupt() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) else if (pending & CAUSEF_IP3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) sb1250_mailbox_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) else if (pending & CAUSEF_IP2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dispatch_ip2();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) spurious_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags