^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/sibyte/sb1250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/sibyte/bcm1480_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/sibyte/bcm1480_scd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/sibyte/sb1250_scd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) unsigned int sb1_pass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned int soc_pass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned int soc_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) EXPORT_SYMBOL(soc_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsigned int periph_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) EXPORT_SYMBOL_GPL(periph_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) unsigned int zbbus_mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) EXPORT_SYMBOL(zbbus_mhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static unsigned int part_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static char *soc_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static char *pass_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int __init setup_bcm1x80_bcm1x55(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) switch (soc_pass) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) case K_SYS_REVISION_BCM1480_S0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) periph_rev = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) pass_str = "S0 (pass1)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) case K_SYS_REVISION_BCM1480_A1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) periph_rev = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) pass_str = "A1 (pass1)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) case K_SYS_REVISION_BCM1480_A2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) periph_rev = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) pass_str = "A2 (pass1)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) case K_SYS_REVISION_BCM1480_A3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) periph_rev = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) pass_str = "A3 (pass1)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) case K_SYS_REVISION_BCM1480_B0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) periph_rev = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) pass_str = "B0 (pass2)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) printk("Unknown %s rev %x\n", soc_str, soc_pass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) periph_rev = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) pass_str = "Unknown Revision";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Setup code likely to be common to all SiByte platforms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int __init sys_rev_decode(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) switch (soc_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) case K_SYS_SOC_TYPE_BCM1x80:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (part_type == K_SYS_PART_BCM1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) soc_str = "BCM1480";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) else if (part_type == K_SYS_PART_BCM1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) soc_str = "BCM1280";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) soc_str = "BCM1x80";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ret = setup_bcm1x80_bcm1x55();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) case K_SYS_SOC_TYPE_BCM1x55:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (part_type == K_SYS_PART_BCM1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) soc_str = "BCM1455";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) else if (part_type == K_SYS_PART_BCM1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) soc_str = "BCM1255";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) soc_str = "BCM1x55";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret = setup_bcm1x80_bcm1x55();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) printk("Unknown part type %x\n", part_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) void __init bcm1480_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) uint64_t sys_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int plldiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) sb1_pass = read_c0_prid() & PRID_REV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) soc_type = SYS_SOC_TYPE(sys_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) part_type = G_SYS_PART(sys_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) soc_pass = G_SYS_REVISION(sys_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (sys_rev_decode()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) printk("Restart after failure to identify SiByte chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) machine_restart(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) zbbus_mhz = ((plldiv >> 1) * 50) + ((plldiv & 1) * 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) printk("Broadcom SiByte %s %s @ %d MHz (SB-1A rev %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) soc_str, pass_str, zbbus_mhz * 2, sb1_pass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) printk("Board type: %s\n", get_system_type());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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