^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel_stat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/irq_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/sibyte/bcm1480_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/sibyte/bcm1480_int.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/sibyte/bcm1480_scd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/sibyte/sb1250_uart.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/sibyte/sb1250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * These are the routines that handle all the low level interrupt stuff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Actions handled here are: initialization of the interrupt map, requesting of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * interrupt lines by handlers, dispatching if interrupts to handlers, probing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * for interrupt lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) extern unsigned long ht_eoi_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Store the CPU id (not the logical number) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int bcm1480_irq_owner[BCM1480_NR_IRQS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static DEFINE_RAW_SPINLOCK(bcm1480_imr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void bcm1480_mask_irq(int cpu, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned long flags, hl_spacing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u64 cur_ints;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) raw_spin_lock_irqsave(&bcm1480_imr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) hl_spacing = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) hl_spacing = BCM1480_IMR_HL_SPACING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) irq -= BCM1480_NR_IRQS_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) cur_ints |= (((u64) 1) << irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) raw_spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) void bcm1480_unmask_irq(int cpu, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned long flags, hl_spacing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u64 cur_ints;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) raw_spin_lock_irqsave(&bcm1480_imr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) hl_spacing = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) hl_spacing = BCM1480_IMR_HL_SPACING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) irq -= BCM1480_NR_IRQS_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) cur_ints &= ~(((u64) 1) << irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) raw_spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int bcm1480_set_affinity(struct irq_data *d, const struct cpumask *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int irq_dirty, irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int i = 0, old_cpu, cpu, int_on, k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u64 cur_ints;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) i = cpumask_first_and(mask, cpu_online_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Convert logical CPU to physical CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) cpu = cpu_logical_map(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Protect against other affinity changers and IMR manipulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) raw_spin_lock_irqsave(&bcm1480_imr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Swizzle each CPU's IMR (but leave the IP selection alone) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) old_cpu = bcm1480_irq_owner[irq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) irq_dirty = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) irq_dirty -= BCM1480_NR_IRQS_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) for (k=0; k<2; k++) { /* Loop through high and low interrupt mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int_on = !(cur_ints & (((u64) 1) << irq_dirty));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (int_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* If it was on, mask it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) cur_ints |= (((u64) 1) << irq_dirty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) bcm1480_irq_owner[irq] = cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (int_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* unmask for the new CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) cur_ints &= ~(((u64) 1) << irq_dirty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) raw_spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void disable_bcm1480_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void enable_bcm1480_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void ack_bcm1480_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int irq_dirty, irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u64 pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * If the interrupt was an HT interrupt, now is the time to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * clear it. NOTE: we assume the HT bridge was set up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * deliver the interrupts to all CPUs (which makes affinity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * changing easier for us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) irq_dirty = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) irq_dirty -= BCM1480_NR_IRQS_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) for (k=0; k<2; k++) { /* Loop through high and low LDT interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) R_BCM1480_IMR_LDT_INTERRUPT_H + (k*BCM1480_IMR_HL_SPACING))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) pending &= ((u64)1 << (irq_dirty));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) for (i=0; i<NR_CPUS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * Clear for all CPUs so an affinity switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * doesn't find an old status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * Generate EOI. For Pass 1 parts, EOI is a nop. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * Pass 2, the LDT world may be edge-triggered, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * this EOI shouldn't hurt. If they are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * level-sensitive, the EOI is required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (ht_eoi_space)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) *(uint32_t *)(ht_eoi_space+(irq<<16)+(7<<2)) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static struct irq_chip bcm1480_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .name = "BCM1480-IMR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .irq_mask_ack = ack_bcm1480_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .irq_mask = disable_bcm1480_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .irq_unmask = enable_bcm1480_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .irq_set_affinity = bcm1480_set_affinity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) void __init init_bcm1480_irqs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) for (i = 0; i < BCM1480_NR_IRQS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) irq_set_chip_and_handler(i, &bcm1480_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) bcm1480_irq_owner[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * init_IRQ is called early in the boot sequence from init/main.c. It
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * is responsible for setting up the interrupt mapper and installing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * handler that will be responsible for dispatching interrupts to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * "right" place.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * For now, map all interrupts to IP[2]. We could save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * some cycles by parceling out system interrupts to different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * IP lines, but keep it simple for bringup. We'll also direct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * all interrupts to a single CPU; we should probably route
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * PCI and LDT to one cpu and everything else to the other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * to balance the load a bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * On the second cpu, everything is set to IP5, which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * ignored, EXCEPT the mailbox interrupt. That one is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * set to IP[2] so it is handled. This is needed so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * can do cross-cpu function calls, as required by SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IMR_IP2_VAL K_BCM1480_INT_MAP_I0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IMR_IP3_VAL K_BCM1480_INT_MAP_I1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define IMR_IP4_VAL K_BCM1480_INT_MAP_I2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define IMR_IP5_VAL K_BCM1480_INT_MAP_I3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define IMR_IP6_VAL K_BCM1480_INT_MAP_I4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) void __init arch_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned int i, cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) STATUSF_IP1 | STATUSF_IP0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* Default everything to IP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Start with _high registers which has no bit 0 interrupt source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) { /* was I0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) for (cpu = 0; cpu < 4; cpu++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) __raw_writeq(IMR_IP2_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) IOADDR(A_BCM1480_IMR_REGISTER(cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (i << 3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Now do _low registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) for (i = 0; i < BCM1480_NR_IRQS_HALF; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) for (cpu = 0; cpu < 4; cpu++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) __raw_writeq(IMR_IP2_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) IOADDR(A_BCM1480_IMR_REGISTER(cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + (i << 3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) init_bcm1480_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * Map the high 16 bits of mailbox_0 registers to IP[3], for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * inter-cpu messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Was I1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) for (cpu = 0; cpu < 4; cpu++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) (K_BCM1480_INT_MBOX_0_0 << 3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Clear the mailboxes. The firmware may leave them dirty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) for (cpu = 0; cpu < 4; cpu++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) __raw_writeq(0xffffffffffffffffULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) __raw_writeq(0xffffffffffffffffULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) tmp = ~((u64) 0) ^ ( (((u64) 1) << K_BCM1480_INT_MBOX_0_0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) for (cpu = 0; cpu < 4; cpu++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) tmp = ~((u64) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) for (cpu = 0; cpu < 4; cpu++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * Note that the timer interrupts are also mapped, but this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * done in bcm1480_time_init(). Also, the profiling driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * does its own management of IP7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Enable necessary IPs, disable the rest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) change_c0_status(ST0_IM, imask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) extern void bcm1480_mailbox_interrupt(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static inline void dispatch_ip2(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned long long mask_h, mask_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unsigned int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned long base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * Default...we've hit an IP[2] interrupt, which means we've got to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * check the 1480 interrupt registers to figure out what to do. Need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * to detect which CPU we're on, now that smp_affinity is supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) base = A_BCM1480_IMR_MAPPER(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) mask_h = __raw_readq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) mask_l = __raw_readq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (mask_h) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (mask_h ^ 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) do_IRQ(fls64(mask_h) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) else if (mask_l)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) do_IRQ(63 + fls64(mask_l));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) asmlinkage void plat_irq_dispatch(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) unsigned int pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) pending = read_c0_cause() & read_c0_status();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (pending & CAUSEF_IP4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) do_IRQ(K_BCM1480_INT_TIMER_0 + cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) else if (pending & CAUSEF_IP3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) bcm1480_mailbox_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) else if (pending & CAUSEF_IP2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dispatch_ip2();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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