Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2006  Ralf Baechle <ralf@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <linux/dma-direct.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <asm/ip32/crime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * Few notes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * 1. CPU sees memory as two chunks: 0-256M@0x0, and the rest @0x40000000+256M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * 2. PCI sees memory as one big chunk @0x0 (or we could use 0x40000000 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  *    native-endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * 3. All other devices see memory as one big chunk at 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * 4. Non-PCI devices will pass NULL as struct device*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * Thus we translate differently, depending on device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RAM_OFFSET_MASK 0x3fffffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	dma_addr_t dma_addr = paddr & RAM_OFFSET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		dma_addr += CRIME_HI_MEM_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	return dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dma_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	phys_addr_t paddr = dma_addr & RAM_OFFSET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	if (dma_addr >= 256*1024*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		paddr += CRIME_HI_MEM_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	return paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }