^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SGI IP30 miscellaneous setup bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004-2007 Stanislaw Skowronek <skylark@unaligned.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * 2007 Joshua Kinard <kumba@gentoo.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * 2009 Johannes Dickgreber <tanzy@gmx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/percpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/smp-ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/sgialib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/sgi/heart.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "ip30-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Structure of accessible HEART registers located in XKPHYS space. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct ip30_heart_regs __iomem *heart_regs = HEART_XKPHYS_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * ARCS will report up to the first 1GB of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * memory if queried. Anything beyond that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * is marked as reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IP30_MAX_PROM_MEMORY _AC(0x40000000, UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Memory in the Octane starts at 512MB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IP30_MEMORY_BASE _AC(0x20000000, UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * If using ARCS to probe for memory, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * remaining memory will start at this offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IP30_REAL_MEMORY_START (IP30_MEMORY_BASE + IP30_MAX_PROM_MEMORY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MEM_SHIFT(x) ((x) >> 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static void __init ip30_mem_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned long total_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) phys_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) phys_addr_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 memcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) total_mem = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) for (i = 0; i < HEART_MEMORY_BANKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) memcfg = __raw_readl(&heart_regs->mem_cfg.l[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (!(memcfg & HEART_MEMCFG_VALID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) addr = memcfg & HEART_MEMCFG_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) addr <<= HEART_MEMCFG_UNIT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) addr += IP30_MEMORY_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) size = memcfg & HEART_MEMCFG_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) size >>= HEART_MEMCFG_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) size += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) size <<= HEART_MEMCFG_UNIT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) total_mem += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (addr >= IP30_REAL_MEMORY_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) memblock_free(addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) else if ((addr + size) > IP30_REAL_MEMORY_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) memblock_free(IP30_REAL_MEMORY_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) size - IP30_MAX_PROM_MEMORY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pr_info("Detected %luMB of physical memory.\n", MEM_SHIFT(total_mem));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * ip30_cpu_time_init - platform time initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void __init ip30_cpu_time_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u64 heart_compare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned int start, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int time_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) heart_compare = (heart_read(&heart_regs->count) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) (HEART_CYCLES_PER_SEC / 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) start = read_c0_count();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) while ((heart_read(&heart_regs->count) - heart_compare) & 0x800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) end = read_c0_count();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) time_diff = (int)end - (int)start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) mips_hpt_frequency = time_diff * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) pr_info("IP30: CPU%d: %d MHz CPU detected.\n", cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) (mips_hpt_frequency * 2) / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) void __init ip30_per_cpu_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Disable all interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) clear_c0_status(ST0_IM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ip30_cpu_time_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ip30_install_ipi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) enable_percpu_irq(IP30_HEART_L0_IRQ, IRQ_TYPE_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) enable_percpu_irq(IP30_HEART_L1_IRQ, IRQ_TYPE_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) enable_percpu_irq(IP30_HEART_L2_IRQ, IRQ_TYPE_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) enable_percpu_irq(IP30_HEART_ERR_IRQ, IRQ_TYPE_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * plat_mem_setup - despite the name, misc setup happens here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) void __init plat_mem_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ip30_mem_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* XXX: Hard lock on /sbin/init if this flag isn't specified. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) prom_flags |= PROM_FLAG_DONT_FREE_TEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) register_smp_ops(&ip30_smp_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ip30_per_cpu_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ioport_resource.start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ioport_resource.end = ~0UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) set_io_port_base(IO_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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