^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/mmzone.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/nodemask.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm/sn/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/sn/addrs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/sn/nmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/sn/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/sn/agent.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define NODE_NUM_CPUS(n) CNODE_NUM_CPUS(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define NODE_NUM_CPUS(n) CPUS_PER_NODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SEND_NMI(_nasid, _slice) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) REMOTE_HUB_S((_nasid), (PI_NMI_A + ((_slice) * PI_NMI_OFFSET)), 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) typedef unsigned long machreg_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static arch_spinlock_t nmi_lock = __ARCH_SPIN_LOCK_UNLOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Let's see what else we need to do here. Set up sp, gp?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void nmi_dump(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void cont_nmi_dump(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) cont_nmi_dump();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void install_cpu_nmi_handler(int slice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) nmi_t *nmi_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) nmi_addr = (nmi_t *)NMI_ADDR(get_nasid(), slice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (nmi_addr->call_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) nmi_addr->magic = NMI_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) nmi_addr->call_addr = (void *)nmi_dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) nmi_addr->call_addr_c =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) (void *)(~((unsigned long)(nmi_addr->call_addr)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) nmi_addr->call_parm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Copy the cpu registers which have been saved in the IP27prom format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * into the eframe format for the node under consideration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) void nmi_cpu_eframe_save(nasid_t nasid, int slice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct reg_struct *nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Get the pointer to the current cpu's register set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) nr = (struct reg_struct *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) (TO_UNCAC(TO_NODE(nasid, IP27_NMI_KREGS_OFFSET)) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) slice * IP27_NMI_KREGS_CPU_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) pr_emerg("NMI nasid %d: slice %d\n", nasid, slice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Saved main processor registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) for (i = 0; i < 32; ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if ((i % 4) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pr_emerg("$%2d :", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pr_cont(" %016lx", nr->gpr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if ((i % 4) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) pr_cont("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pr_emerg("Hi : (value lost)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) pr_emerg("Lo : (value lost)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * Saved cp0 registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pr_emerg("epc : %016lx %pS\n", nr->epc, (void *)nr->epc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) pr_emerg("%s\n", print_tainted());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) pr_emerg("ErrEPC: %016lx %pS\n", nr->error_epc, (void *)nr->error_epc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) pr_emerg("ra : %016lx %pS\n", nr->gpr[31], (void *)nr->gpr[31]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) pr_emerg("Status: %08lx ", nr->sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (nr->sr & ST0_KX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) pr_cont("KX ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (nr->sr & ST0_SX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pr_cont("SX ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (nr->sr & ST0_UX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) pr_cont("UX ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) switch (nr->sr & ST0_KSU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) case KSU_USER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) pr_cont("USER ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) case KSU_SUPERVISOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) pr_cont("SUPERVISOR ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) case KSU_KERNEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pr_cont("KERNEL ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pr_cont("BAD_MODE ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (nr->sr & ST0_ERL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) pr_cont("ERL ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (nr->sr & ST0_EXL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) pr_cont("EXL ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (nr->sr & ST0_IE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) pr_cont("IE ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) pr_cont("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) pr_emerg("Cause : %08lx\n", nr->cause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) pr_emerg("PrId : %08x\n", read_c0_prid());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) pr_emerg("BadVA : %016lx\n", nr->badva);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) pr_emerg("CErr : %016lx\n", nr->cache_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) pr_emerg("NMI_SR: %016lx\n", nr->nmi_sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) pr_emerg("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) void nmi_dump_hub_irq(nasid_t nasid, int slice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u64 mask0, mask1, pend0, pend1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (slice == 0) { /* Slice A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mask0 = REMOTE_HUB_L(nasid, PI_INT_MASK0_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) } else { /* Slice B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) mask0 = REMOTE_HUB_L(nasid, PI_INT_MASK0_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) pend0 = REMOTE_HUB_L(nasid, PI_INT_PEND0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) pend1 = REMOTE_HUB_L(nasid, PI_INT_PEND1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) pr_emerg("PI_INT_MASK0: %16llx PI_INT_MASK1: %16llx\n", mask0, mask1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) pr_emerg("PI_INT_PEND0: %16llx PI_INT_PEND1: %16llx\n", pend0, pend1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) pr_emerg("\n\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * Copy the cpu registers which have been saved in the IP27prom format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * into the eframe format for the node under consideration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) void nmi_node_eframe_save(nasid_t nasid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int slice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (nasid == INVALID_NASID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Save the registers into eframe for each cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) for (slice = 0; slice < NODE_NUM_CPUS(slice); slice++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) nmi_cpu_eframe_save(nasid, slice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) nmi_dump_hub_irq(nasid, slice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * Save the nmi cpu registers for all cpus in the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) nmi_eframes_save(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) nasid_t nasid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) for_each_online_node(nasid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) nmi_node_eframe_save(nasid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) cont_nmi_dump(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #ifndef REAL_NMI_SIGNAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static atomic_t nmied_cpus = ATOMIC_INIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) atomic_inc(&nmied_cpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * Only allow 1 cpu to proceed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) arch_spin_lock(&nmi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #ifdef REAL_NMI_SIGNAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * Wait up to 15 seconds for the other cpus to respond to the NMI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * If a cpu has not responded after 10 sec, send it 1 additional NMI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * This is for 2 reasons:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * - sometimes a MMSC fail to NMI all cpus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * - on 512p SN0 system, the MMSC will only send NMIs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * half the cpus. Unfortunately, we don't know which cpus may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * NMIed - it depends on how the site chooses to configure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * Note: it has been measure that it takes the MMSC up to 2.3 secs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * send NMIs to all cpus on a 256p system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) for (i=0; i < 1500; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) for_each_online_node(node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (NODEPDA(node)->dump_count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (node == MAX_NUMNODES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (i == 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) for_each_online_node(node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (NODEPDA(node)->dump_count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) cpu = cpumask_first(cpumask_of_node(node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) for (n=0; n < CNODE_NUM_CPUS(node); cpu++, n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) CPUMASK_SETB(nmied_cpus, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * cputonasid, cputoslice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * needs kernel cpuid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) SEND_NMI((cputonasid(cpu)), (cputoslice(cpu)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) udelay(10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) while (atomic_read(&nmied_cpus) != num_online_cpus());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * Save the nmi cpu registers for all cpu in the eframe format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) nmi_eframes_save();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) LOCAL_HUB_S(NI_PORT_RESET, NPR_PORTRESET | NPR_LOCALRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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