^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ip27-irq.c: Highlevel interrupt handling for IP27 architecture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1999 - 2001 Kanoj Sarcar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/irq_cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/sn/addrs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/sn/agent.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/sn/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/sn/intr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/sn/irq_alloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct hub_irq_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u64 *irq_mask[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) cpuid_t cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static DECLARE_BITMAP(hub_irq_map, IP27_HUB_IRQ_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static DEFINE_PER_CPU(unsigned long [2], irq_enable_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static inline int alloc_level(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) again:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) level = find_first_zero_bit(hub_irq_map, IP27_HUB_IRQ_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (level >= IP27_HUB_IRQ_COUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (test_and_set_bit(level, hub_irq_map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) goto again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static void enable_hub_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct hub_irq_data *hd = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) set_bit(d->hwirq, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) __raw_writeq(mask[0], hd->irq_mask[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) __raw_writeq(mask[1], hd->irq_mask[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static void disable_hub_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct hub_irq_data *hd = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) clear_bit(d->hwirq, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __raw_writeq(mask[0], hd->irq_mask[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __raw_writeq(mask[1], hd->irq_mask[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static void setup_hub_mask(struct hub_irq_data *hd, const struct cpumask *mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) nasid_t nasid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) cpu = cpumask_first_and(mask, cpu_online_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (cpu >= nr_cpu_ids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) cpu = cpumask_any(cpu_online_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) nasid = cpu_to_node(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) hd->cpu = cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (!cputoslice(cpu)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) hd->irq_mask[0] = REMOTE_HUB_PTR(nasid, PI_INT_MASK0_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) hd->irq_mask[1] = REMOTE_HUB_PTR(nasid, PI_INT_MASK1_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) hd->irq_mask[0] = REMOTE_HUB_PTR(nasid, PI_INT_MASK0_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) hd->irq_mask[1] = REMOTE_HUB_PTR(nasid, PI_INT_MASK1_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int set_affinity_hub_irq(struct irq_data *d, const struct cpumask *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct hub_irq_data *hd = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (!hd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (irqd_is_started(d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) disable_hub_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) setup_hub_mask(hd, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (irqd_is_started(d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) enable_hub_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) irq_data_update_effective_affinity(d, cpumask_of(hd->cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static struct irq_chip hub_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .name = "HUB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .irq_mask = disable_hub_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .irq_unmask = enable_hub_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .irq_set_affinity = set_affinity_hub_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int hub_domain_alloc(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int nr_irqs, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct irq_alloc_info *info = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct hub_irq_data *hd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct hub_data *hub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct irq_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int swlevel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (nr_irqs > 1 || !info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) hd = kzalloc(sizeof(*hd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (!hd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) swlevel = alloc_level();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (unlikely(swlevel < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) kfree(hd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) irq_domain_set_info(domain, virq, swlevel, &hub_irq_type, hd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) handle_level_irq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* use CPU connected to nearest hub */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) hub = hub_data(info->nasid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) setup_hub_mask(hd, &hub->h_cpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) info->nasid = cpu_to_node(hd->cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Make sure it's not already pending when we connect it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) REMOTE_HUB_CLR_INTR(info->nasid, swlevel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) desc = irq_to_desc(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) desc->irq_common_data.node = info->nasid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) cpumask_copy(desc->irq_common_data.affinity, &hub->h_cpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void hub_domain_free(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned int virq, unsigned int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct irq_data *irqd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (nr_irqs > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) irqd = irq_domain_get_irq_data(domain, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (irqd && irqd->chip_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) kfree(irqd->chip_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const struct irq_domain_ops hub_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .alloc = hub_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .free = hub_domain_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * This code is unnecessarily complex, because we do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * intr enabling. Basically, once we grab the set of intrs we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * to service, we must mask _all_ these interrupts; firstly, to make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * sure the same intr does not intr again, causing recursion that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * can lead to stack overflow. Secondly, we can not just mask the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * one intr we are do_IRQing, because the non-masked intrs in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * first set might intr again, causing multiple servicings of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * same intr. This effect is mostly seen for intercpu intrs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * Kanoj 05.13.00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void ip27_do_irq_mask0(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) cpuid_t cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned long *mask = per_cpu(irq_enable_mask, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u64 pend0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* copied from Irix intpend0() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pend0 = LOCAL_HUB_L(PI_INT_PEND0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pend0 &= mask[0]; /* Pick intrs we should look at */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (!pend0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (pend0 & (1UL << CPU_RESCHED_A_IRQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) LOCAL_HUB_CLR_INTR(CPU_RESCHED_A_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) scheduler_ipi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) } else if (pend0 & (1UL << CPU_RESCHED_B_IRQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) LOCAL_HUB_CLR_INTR(CPU_RESCHED_B_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) scheduler_ipi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) } else if (pend0 & (1UL << CPU_CALL_A_IRQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) generic_smp_call_function_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) } else if (pend0 & (1UL << CPU_CALL_B_IRQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) LOCAL_HUB_CLR_INTR(CPU_CALL_B_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) generic_smp_call_function_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) domain = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) irq = irq_linear_revmap(domain, __ffs(pend0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) spurious_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) LOCAL_HUB_L(PI_INT_PEND0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static void ip27_do_irq_mask1(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) cpuid_t cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned long *mask = per_cpu(irq_enable_mask, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u64 pend1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* copied from Irix intpend0() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) pend1 = LOCAL_HUB_L(PI_INT_PEND1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) pend1 &= mask[1]; /* Pick intrs we should look at */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (!pend1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) domain = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) irq = irq_linear_revmap(domain, __ffs(pend1) + 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) spurious_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) LOCAL_HUB_L(PI_INT_PEND1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) void install_ipi(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned long *mask = per_cpu(irq_enable_mask, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int slice = LOCAL_HUB_L(PI_CPU_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int resched, call;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) resched = CPU_RESCHED_A_IRQ + slice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) set_bit(resched, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) LOCAL_HUB_CLR_INTR(resched);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) call = CPU_CALL_A_IRQ + slice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) set_bit(call, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) LOCAL_HUB_CLR_INTR(call);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (slice == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) LOCAL_HUB_S(PI_INT_MASK0_A, mask[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) LOCAL_HUB_S(PI_INT_MASK1_A, mask[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) LOCAL_HUB_S(PI_INT_MASK0_B, mask[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) LOCAL_HUB_S(PI_INT_MASK1_B, mask[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) void __init arch_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct fwnode_handle *fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) mips_cpu_irq_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * Some interrupts are reserved by hardware or by software convention.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * Mark these as reserved right away so they won't be used accidentally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) for (i = 0; i <= CPU_CALL_B_IRQ; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) set_bit(i, hub_irq_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) for (i = NI_BRDCAST_ERR_A; i <= MSC_PANIC_INTR; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) set_bit(i, hub_irq_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) fn = irq_domain_alloc_named_fwnode("HUB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) WARN_ON(fn == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (!fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) domain = irq_domain_create_linear(fn, IP27_HUB_IRQ_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) &hub_domain_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) WARN_ON(domain == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (!domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) irq_set_default_host(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) irq_set_percpu_devid(IP27_HUB_PEND0_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) irq_set_chained_handler_and_data(IP27_HUB_PEND0_IRQ, ip27_do_irq_mask0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) irq_set_percpu_devid(IP27_HUB_PEND1_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) irq_set_chained_handler_and_data(IP27_HUB_PEND1_IRQ, ip27_do_irq_mask1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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