^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Time operations for IP22 machines. Original code may come from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Ralf Baechle or David S. Miller (sorry guys, i'm really not sure)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2001 by Ladislav Michl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2003, 06 Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/i8253.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel_stat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/ftrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/sgialib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/sgi/ioc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/sgi/hpc3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/sgi/ip22.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static unsigned long dosample(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 ct0, ct1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u8 msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Start the counter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) SGINT_TCWORD_MRGEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) sgint->tcnt2 = SGINT_TCSAMP_COUNTER & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) sgint->tcnt2 = SGINT_TCSAMP_COUNTER >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Get initial counter invariant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ct0 = read_c0_count();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Latch and spin until top byte of counter2 is zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) writeb(SGINT_TCWORD_CNT2 | SGINT_TCWORD_CLAT, &sgint->tcword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) (void) readb(&sgint->tcnt2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) msb = readb(&sgint->tcnt2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ct1 = read_c0_count();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) } while (msb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Stop the counter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) writeb(SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL | SGINT_TCWORD_MSWST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) &sgint->tcword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Return the difference, this is how far the r4k counter increments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * for every 1/HZ seconds. We round off the nearest 1 MHz of master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * clock (= 1000000 / HZ / 2).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return (ct1 - ct0) / (500000/HZ) * (500000/HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Here we need to calibrate the cycle counter to at least be close.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __init void plat_time_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned long r4k_ticks[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned long r4k_tick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Figure out the r4k offset, the algorithm is very simple and works in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * _all_ cases as long as the 8254 counter register itself works ok (as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * an interrupt driving timer it does not because of bug, this is why
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * we are using the onchip r4k counter/compare register to serve this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * purpose, but for r4k_offset calculation it will work ok for us).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * There are other very complicated ways of performing this calculation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * but this one works just fine so I am not going to futz around. ;-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) printk(KERN_INFO "Calibrating system timer... ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) dosample(); /* Prime cache. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) dosample(); /* Prime cache. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Zero is NOT an option. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) r4k_ticks[0] = dosample();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) } while (!r4k_ticks[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) r4k_ticks[1] = dosample();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) } while (!r4k_ticks[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (r4k_ticks[0] != r4k_ticks[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) printk("warning: timer counts differ, retrying... ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) r4k_ticks[2] = dosample();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (r4k_ticks[2] == r4k_ticks[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) || r4k_ticks[2] == r4k_ticks[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) r4k_tick = r4k_ticks[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) printk("disagreement, using average... ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) r4k_tick = (r4k_ticks[0] + r4k_ticks[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) + r4k_ticks[2]) / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) r4k_tick = r4k_ticks[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) printk("%d [%d.%04d MHz CPU]\n", (int) r4k_tick,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) (int) (r4k_tick / (500000 / HZ)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) (int) (r4k_tick % (500000 / HZ)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) mips_hpt_frequency = r4k_tick * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (ip22_is_fullhouse())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) setup_pit_timer();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Generic SGI handler for (spurious) 8254 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) void __irq_entry indy_8254timer_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int irq = SGI_8254_0_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ULONG cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) char c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) irq_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) kstat_incr_irq_this_cpu(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) printk(KERN_ALERT "Oops, got 8254 interrupt.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ArcRead(0, &c, 1, &cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ArcEnterInteractiveMode();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) irq_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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