^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ip22-nvram.c: NVRAM and serial EEPROM handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/sgi/hpc3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/sgi/ip22.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* Control opcode for serial eeprom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define EEPROM_READ 0xc000 /* serial memory read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define EEPROM_WEN 0x9800 /* write enable before prog modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define EEPROM_WRITE 0xa000 /* serial memory write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define EEPROM_WRALL 0x8800 /* write all registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define EEPROM_WDS 0x8000 /* disable all programming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define EEPROM_PRREAD 0xc000 /* read protect register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define EEPROM_PREN 0x9800 /* enable protect register mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define EEPROM_PRCLEAR 0xffff /* clear protect register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define EEPROM_PRWRITE 0xa000 /* write protect register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define EEPROM_PRDS 0x8000 /* disable protect register, forever */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define EEPROM_EPROT 0x01 /* Protect register enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EEPROM_CSEL 0x02 /* Chip select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define EEPROM_ECLK 0x04 /* EEPROM clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define EEPROM_DATO 0x08 /* Data out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define EEPROM_DATI 0x10 /* Data in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* We need to use these functions early... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define delay() ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int x; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) for (x=0; x<100000; x++) __asm__ __volatile__(""); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define eeprom_cs_on(ptr) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) delay(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define eeprom_cs_off(ptr) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BITS_IN_COMMAND 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * clock in the nvram command and the register number. For the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * national semiconductor nv ram chip the op code is 3 bits and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * the address is 6/8 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static inline void eeprom_cmd(unsigned int *ctrl, unsigned cmd, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned short ser_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ser_cmd = cmd | (reg << (16 - BITS_IN_COMMAND));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) for (i = 0; i < BITS_IN_COMMAND; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (ser_cmd & (1<<15)) /* if high order bit set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) __raw_writel(__raw_readl(ctrl) | EEPROM_DATO, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __raw_writel(__raw_readl(ctrl) & ~EEPROM_DATO, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) __raw_writel(__raw_readl(ctrl) & ~EEPROM_ECLK, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) delay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) delay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ser_cmd <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* see data sheet timing diagram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __raw_writel(__raw_readl(ctrl) & ~EEPROM_DATO, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned short res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __raw_writel(__raw_readl(ctrl) & ~EEPROM_EPROT, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) eeprom_cs_on(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) eeprom_cmd(ctrl, EEPROM_READ, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* clock the data ouf of serial mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __raw_writel(__raw_readl(ctrl) & ~EEPROM_ECLK, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) delay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) delay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) res <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (__raw_readl(ctrl) & EEPROM_DATI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) res |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) eeprom_cs_off(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) EXPORT_SYMBOL(ip22_eeprom_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Read specified register from main NVRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned short ip22_nvram_read(int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (ip22_is_fullhouse())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* IP22 (Indigo2 aka FullHouse) stores env variables into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * 93CS56 Microwire Bus EEPROM 2048 Bit (128x16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return ip22_eeprom_read(&hpc3c0->eeprom, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned short tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* IP24 (Indy aka Guiness) uses DS1386 8K version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) reg <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) tmp = hpc3c0->bbram[reg++] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return (tmp << 8) | (hpc3c0->bbram[reg] & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) EXPORT_SYMBOL(ip22_nvram_read);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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