^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ip22-mc.c: Routines for manipulating SGI Memory Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - Indigo2 changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2004 Peter Fuerst (pf@net.alphadv.de) - IP28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/sgialib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/sgi/mc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/sgi/hpc3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/sgi/ip22.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct sgimc_regs *sgimc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) EXPORT_SYMBOL(sgimc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static inline unsigned long get_bank_addr(unsigned int memconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) return (memconfig & SGIMC_MCONFIG_BASEADDR) << ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 24 : 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static inline unsigned long get_bank_size(unsigned int memconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return ((memconfig & SGIMC_MCONFIG_RMASK) + 0x0100) << ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 16 : 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static inline unsigned int get_bank_config(int bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int res = bank > 1 ? sgimc->mconfig1 : sgimc->mconfig0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return bank % 2 ? res & 0xffff : res >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #if defined(CONFIG_SGI_IP28) || defined(CONFIG_32BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static void __init probe_memory(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* prom detects all usable memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Detect installed memory, which PROM misses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static void __init probe_memory(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned long addr, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) printk(KERN_INFO "MC: Probing memory configuration:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int tmp = get_bank_config(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (!(tmp & SGIMC_MCONFIG_BVALID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) size = get_bank_size(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) addr = get_bank_addr(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) printk(KERN_INFO " bank%d: %3ldM @ %08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) i, size / 1024 / 1024, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (addr >= SGIMC_SEG1_BADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) memblock_add(addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) void __init sgimc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* ioremap can't fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) sgimc = (struct sgimc_regs *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ioremap(SGIMC_BASE, sizeof(struct sgimc_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) printk(KERN_INFO "MC: SGI memory controller Revision %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) (int) sgimc->systemid & SGIMC_SYSID_MASKREV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Place the MC into a known state. This must be done before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * interrupts are first enabled etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Step 0: Make sure we turn off the watchdog in case it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * still running (which might be the case after a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * soft reboot).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) tmp = sgimc->cpuctrl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) tmp &= ~SGIMC_CCTRL0_WDOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) sgimc->cpuctrl0 = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Step 1: The CPU/GIO error status registers will not latch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * up a new error status until the register has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * cleared by the cpu. These status registers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * cleared by writing any value to them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) sgimc->cstat = sgimc->gstat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Step 2: Enable all parity checking in cpu control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* don't touch parity settings for IP28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) tmp = sgimc->cpuctrl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #ifndef CONFIG_SGI_IP28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) tmp |= SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) tmp |= SGIMC_CCTRL0_R4KNOCHKPARR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) sgimc->cpuctrl0 = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Step 3: Setup the MC write buffer depth, this is controlled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * in cpu control register 1 in the lower 4 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) tmp = sgimc->cpuctrl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) tmp &= ~0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) tmp |= 0xd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) sgimc->cpuctrl1 = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Step 4: Initialize the RPSS divider register to run as fast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * as it can correctly operate. The register is laid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * out as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * ----------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * | RESERVED | INCREMENT | DIVIDER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * ----------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * 31 16 15 8 7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * DIVIDER determines how often a 'tick' happens,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * INCREMENT determines by how the RPSS increment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * registers value increases at each 'tick'. Thus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) sgimc->divider = 0x101;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Step 5: Initialize GIO64 arbitrator configuration register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * NOTE: HPC init code in sgihpc_init() must run before us because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * we need to know Guiness vs. FullHouse and the board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * revision on this machine. You have been warned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* First the basic invariants across all GIO64 implementations. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) tmp = sgimc->giopar & SGIMC_GIOPAR_GFX64; /* keep gfx 64bit settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) tmp |= SGIMC_GIOPAR_HPC64; /* All 1st HPC's interface at 64bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) tmp |= SGIMC_GIOPAR_ONEBUS; /* Only one physical GIO bus exists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (ip22_is_fullhouse()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Fullhouse specific settings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (SGIOC_SYSID_BOARDREV(sgioc->sysid) < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) tmp |= SGIMC_GIOPAR_HPC264; /* 2nd HPC at 64bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp0 pipelines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) tmp |= SGIMC_GIOPAR_MASTEREXP1; /* exp1 masters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) tmp |= SGIMC_GIOPAR_RTIMEEXP0; /* exp0 is realtime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) tmp |= SGIMC_GIOPAR_HPC264; /* 2nd HPC 64bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp[01] pipelined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) tmp |= SGIMC_GIOPAR_PLINEEXP1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Guiness specific settings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) tmp |= SGIMC_GIOPAR_EISA64; /* MC talks to EISA at 64bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA bus can act as master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) sgimc->giopar = tmp; /* poof */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) probe_memory();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #ifdef CONFIG_SGI_IP28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) void __init prom_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 mconfig1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * because ARCS accesses memory uncached we wait until ARCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * isn't needed any longer, before we switch from slow to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * normal mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) spin_lock_irqsave(&lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) mconfig1 = sgimc->mconfig1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* map ECC register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) sgimc->mconfig1 = (mconfig1 & 0xffff0000) | 0x2060;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* switch to normal mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) *(unsigned long *)PHYS_TO_XKSEG_UNCACHED(0x60000000) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* reduce WR_COL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) sgimc->cmacc = (sgimc->cmacc & ~0xf) | 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* restore old config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) sgimc->mconfig1 = mconfig1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) spin_unlock_irqrestore(&lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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