Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * setup.c - boot time setup code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <asm/bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/mach-rc32434/rb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/mach-rc32434/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct pci_reg __iomem *pci_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) EXPORT_SYMBOL(pci_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static struct resource pci0_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		.name = "pci_reg0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		.start = PCI0_BASE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		.end = PCI0_BASE_ADDR + sizeof(struct pci_reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		.flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static void rb_machine_restart(char *command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	/* just jump to the reset vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	writel(0x80000001, IDT434_REG_BASE + RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	((void (*)(void)) KSEG1ADDR(0x1FC00000u))();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void rb_machine_halt(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	for (;;)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void __init plat_mem_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	_machine_restart = rb_machine_restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	_machine_halt = rb_machine_halt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	pm_power_off = rb_machine_halt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	set_io_port_base(KSEG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	pci_reg = ioremap(pci0_res[0].start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 				pci0_res[0].end - pci0_res[0].start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	if (!pci_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		printk(KERN_ERR "Could not remap PCI registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	val = __raw_readl(&pci_reg->pcic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	val &= 0xFFFFFF7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	__raw_writel(val, (void *)&pci_reg->pcic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	/* Enable PCI interrupts in EPLD Mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	*epld_mask = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	*(epld_mask + 1) = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	write_c0_wired(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) const char *get_system_type(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	switch (mips_machtype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	case MACH_MIKROTIK_RB532A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 		return "Mikrotik RB532A";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 		return "Mikrotik RB532";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }