^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Parts of this file are based on Ralink's 2.6.21 BSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2013 John Crispin <john@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/mach-ralink/ralink_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/mach-ralink/rt3883.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/mach-ralink/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static struct rt2880_pmx_func uartf_func[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna g", 0, 35, 3) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static struct rt2880_pmx_func pci_func[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) FUNC("pci-dev", 0, 40, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) FUNC("pci-host2", 1, 40, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) FUNC("pci-host1", 2, 40, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) FUNC("pci-fnc", 3, 40, 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static struct rt2880_pmx_func ge2_func[] = { FUNC("ge2", 0, 84, 12) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static struct rt2880_pmx_group rt3883_pinmux_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) RT3883_GPIO_MODE_UART0_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) RT3883_GPIO_MODE_PCI_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) void __init ralink_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned long cpu_rate, sys_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 syscfg0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 clksel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 ddr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) RT3883_SYSCFG0_CPUCLK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) switch (clksel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) case RT3883_SYSCFG0_CPUCLK_250:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) cpu_rate = 250000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) sys_rate = (ddr2) ? 125000000 : 83000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) case RT3883_SYSCFG0_CPUCLK_384:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) cpu_rate = 384000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) sys_rate = (ddr2) ? 128000000 : 96000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) case RT3883_SYSCFG0_CPUCLK_480:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) cpu_rate = 480000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) sys_rate = (ddr2) ? 160000000 : 120000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) case RT3883_SYSCFG0_CPUCLK_500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) cpu_rate = 500000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) sys_rate = (ddr2) ? 166000000 : 125000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ralink_clk_add("cpu", cpu_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ralink_clk_add("10000100.timer", sys_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ralink_clk_add("10000120.watchdog", sys_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ralink_clk_add("10000500.uart", 40000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ralink_clk_add("10000900.i2c", 40000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ralink_clk_add("10000a00.i2s", 40000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ralink_clk_add("10000b00.spi", sys_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ralink_clk_add("10000b40.spi", sys_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ralink_clk_add("10000c00.uartlite", 40000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ralink_clk_add("10100000.ethernet", sys_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ralink_clk_add("10180000.wmac", 40000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void __init ralink_of_remap(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (!rt_sysc_membase || !rt_memc_membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) panic("Failed to remap core resources");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) void prom_soc_init(struct ralink_soc_info *soc_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 n0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 n1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) id = __raw_readl(sysc + RT3883_SYSC_REG_REVID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) soc_info->compatible = "ralink,rt3883-soc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) name = "RT3883";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) panic("rt3883: unknown SoC, n0:%08x n1:%08x", n0, n1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "Ralink %s ver:%u eco:%u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) (id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) (id & RT3883_REVID_ECO_ID_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) soc_info->mem_base = RT3883_SDRAM_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) rt2880_pinmux_data = rt3883_pinmux_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ralink_soc = RT3883_SOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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