Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Parts of this file are based on Ralink's 2.6.21 BSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2013 John Crispin <john@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/mach-ralink/ralink_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/mach-ralink/rt305x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/mach-ralink/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) static struct rt2880_pmx_func i2c_func[] =  { FUNC("i2c", 0, 1, 2) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) static struct rt2880_pmx_func uartf_func[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static struct rt2880_pmx_func rt5350_cs1_func[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	FUNC("spi_cs1", 0, 27, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	FUNC("wdg_cs1", 1, 27, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static struct rt2880_pmx_func rt3352_rgmii_func[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	FUNC("rgmii", 0, 24, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static struct rt2880_pmx_func rt3352_cs1_func[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	FUNC("spi_cs1", 0, 45, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	FUNC("wdg_cs1", 1, 45, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static struct rt2880_pmx_group rt3050_pinmux_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		RT305X_GPIO_MODE_UART0_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	{ 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static struct rt2880_pmx_group rt3352_pinmux_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		RT305X_GPIO_MODE_UART0_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	GRP("spi_cs1", rt3352_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	{ 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static struct rt2880_pmx_group rt5350_pinmux_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		RT305X_GPIO_MODE_UART0_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	GRP("spi_cs1", rt5350_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	{ 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static unsigned long rt5350_get_mem_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	unsigned long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		RT5350_SYSCFG0_DRAM_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	switch (t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	case RT5350_SYSCFG0_DRAM_SIZE_2M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		ret = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	case RT5350_SYSCFG0_DRAM_SIZE_8M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		ret = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	case RT5350_SYSCFG0_DRAM_SIZE_16M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		ret = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	case RT5350_SYSCFG0_DRAM_SIZE_32M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		ret = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	case RT5350_SYSCFG0_DRAM_SIZE_64M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		ret = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		panic("rt5350: invalid DRAM size: %u", t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) void __init ralink_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	unsigned long wmac_rate = 40000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (soc_is_rt305x() || soc_is_rt3350()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		     RT305X_SYSCFG_CPUCLK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		switch (t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		case RT305X_SYSCFG_CPUCLK_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			cpu_rate = 320000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		case RT305X_SYSCFG_CPUCLK_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			cpu_rate = 384000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	} else if (soc_is_rt3352()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		     RT3352_SYSCFG0_CPUCLK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		switch (t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		case RT3352_SYSCFG0_CPUCLK_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			cpu_rate = 384000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		case RT3352_SYSCFG0_CPUCLK_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			cpu_rate = 400000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		sys_rate = wdt_rate = cpu_rate / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		uart_rate = 40000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	} else if (soc_is_rt5350()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		     RT5350_SYSCFG0_CPUCLK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		switch (t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		case RT5350_SYSCFG0_CPUCLK_360:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			cpu_rate = 360000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			sys_rate = cpu_rate / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		case RT5350_SYSCFG0_CPUCLK_320:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			cpu_rate = 320000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			sys_rate = cpu_rate / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		case RT5350_SYSCFG0_CPUCLK_300:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			cpu_rate = 300000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			sys_rate = cpu_rate / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		uart_rate = 40000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		wdt_rate = sys_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (soc_is_rt3352() || soc_is_rt5350()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		if (!(val & RT3352_CLKCFG0_XTAL_SEL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			wmac_rate = 20000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	ralink_clk_add("cpu", cpu_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	ralink_clk_add("sys", sys_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	ralink_clk_add("10000900.i2c", uart_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	ralink_clk_add("10000a00.i2s", uart_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	ralink_clk_add("10000b00.spi", sys_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	ralink_clk_add("10000b40.spi", sys_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	ralink_clk_add("10000100.timer", wdt_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	ralink_clk_add("10000120.watchdog", wdt_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	ralink_clk_add("10000500.uart", uart_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	ralink_clk_add("10000c00.uartlite", uart_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	ralink_clk_add("10100000.ethernet", sys_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	ralink_clk_add("10180000.wmac", wmac_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) void __init ralink_of_remap(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (!rt_sysc_membase || !rt_memc_membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		panic("Failed to remap core resources");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) void prom_soc_init(struct ralink_soc_info *soc_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	unsigned char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	u32 n0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	u32 n1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		unsigned long icache_sets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		icache_sets = (read_c0_config1() >> 22) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		if (icache_sets == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			ralink_soc = RT305X_SOC_RT3050;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			name = "RT3050";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			soc_info->compatible = "ralink,rt3050-soc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			ralink_soc = RT305X_SOC_RT3052;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			name = "RT3052";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			soc_info->compatible = "ralink,rt3052-soc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	} else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		ralink_soc = RT305X_SOC_RT3350;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		name = "RT3350";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		soc_info->compatible = "ralink,rt3350-soc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	} else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		ralink_soc = RT305X_SOC_RT3352;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		name = "RT3352";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		soc_info->compatible = "ralink,rt3352-soc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	} else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		ralink_soc = RT305X_SOC_RT5350;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		name = "RT5350";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		soc_info->compatible = "ralink,rt5350-soc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		panic("rt305x: unknown SoC, n0:%08x n1:%08x", n0, n1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		"Ralink %s id:%u rev:%u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		(id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		(id & CHIP_ID_REV_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	soc_info->mem_base = RT305X_SDRAM_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	if (soc_is_rt5350()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		soc_info->mem_size = rt5350_get_mem_size();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		rt2880_pinmux_data = rt5350_pinmux_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	} else if (soc_is_rt305x() || soc_is_rt3350()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		rt2880_pinmux_data = rt3050_pinmux_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	} else if (soc_is_rt3352()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		rt2880_pinmux_data = rt3352_pinmux_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }