^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Parts of this file are based on Ralink's 2.6.21 BSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2013 John Crispin <john@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/mach-ralink/ralink_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/mach-ralink/rt288x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/mach-ralink/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 8) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static struct rt2880_pmx_func pci_func[] = { FUNC("pci", 0, 40, 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static struct rt2880_pmx_group rt2880_pinmux_data_act[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) GRP("jtag", jtag_func, 1, RT2880_GPIO_MODE_JTAG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) GRP("mdio", mdio_func, 1, RT2880_GPIO_MODE_MDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) GRP("sdram", sdram_func, 1, RT2880_GPIO_MODE_SDRAM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) GRP("pci", pci_func, 1, RT2880_GPIO_MODE_PCI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) void __init ralink_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned long cpu_rate, wmac_rate = 40000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) switch (t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) case SYSTEM_CONFIG_CPUCLK_250:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) cpu_rate = 250000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) case SYSTEM_CONFIG_CPUCLK_266:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) cpu_rate = 266666667;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) case SYSTEM_CONFIG_CPUCLK_280:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) cpu_rate = 280000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) case SYSTEM_CONFIG_CPUCLK_300:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) cpu_rate = 300000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ralink_clk_add("cpu", cpu_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ralink_clk_add("300100.timer", cpu_rate / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ralink_clk_add("300120.watchdog", cpu_rate / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ralink_clk_add("300500.uart", cpu_rate / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ralink_clk_add("300900.i2c", cpu_rate / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ralink_clk_add("300c00.uartlite", cpu_rate / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ralink_clk_add("400000.ethernet", cpu_rate / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ralink_clk_add("480000.wmac", wmac_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) void __init ralink_of_remap(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (!rt_sysc_membase || !rt_memc_membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) panic("Failed to remap core resources");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) void prom_soc_init(struct ralink_soc_info *soc_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 n0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 n1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) soc_info->compatible = "ralink,r2880-soc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) name = "RT2880";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "Ralink %s id:%u rev:%u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) (id & CHIP_ID_REV_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) soc_info->mem_base = RT2880_SDRAM_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) rt2880_pinmux_data = rt2880_pinmux_data_act;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ralink_soc = RT2880_SOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags