^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2015 Nikolay Martynov <mar.kolya@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 John Crispin <john@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/sys_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/smp-ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/mips-cps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/mach-ralink/ralink_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/mach-ralink/mt7621.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MT7621_GPIO_MODE_UART1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MT7621_GPIO_MODE_I2C 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MT7621_GPIO_MODE_UART3_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MT7621_GPIO_MODE_UART3_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MT7621_GPIO_MODE_UART3_GPIO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MT7621_GPIO_MODE_UART2_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MT7621_GPIO_MODE_UART2_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MT7621_GPIO_MODE_UART2_GPIO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MT7621_GPIO_MODE_JTAG 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MT7621_GPIO_MODE_WDT_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MT7621_GPIO_MODE_WDT_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MT7621_GPIO_MODE_WDT_GPIO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MT7621_GPIO_MODE_PCIE_RST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MT7621_GPIO_MODE_PCIE_REF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MT7621_GPIO_MODE_PCIE_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MT7621_GPIO_MODE_PCIE_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MT7621_GPIO_MODE_PCIE_GPIO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MT7621_GPIO_MODE_MDIO_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MT7621_GPIO_MODE_MDIO_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MT7621_GPIO_MODE_MDIO_GPIO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MT7621_GPIO_MODE_RGMII1 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MT7621_GPIO_MODE_RGMII2 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MT7621_GPIO_MODE_SPI_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MT7621_GPIO_MODE_SPI_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MT7621_GPIO_MODE_SPI_GPIO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MT7621_GPIO_MODE_SDHCI_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MT7621_GPIO_MODE_SDHCI_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MT7621_GPIO_MODE_SDHCI_GPIO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static struct rt2880_pmx_func uart3_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) FUNC("uart3", 0, 5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) FUNC("i2s", 2, 5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) FUNC("spdif3", 3, 5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static struct rt2880_pmx_func uart2_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) FUNC("uart2", 0, 9, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) FUNC("pcm", 2, 9, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) FUNC("spdif2", 3, 9, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct rt2880_pmx_func wdt_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) FUNC("wdt rst", 0, 18, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) FUNC("wdt refclk", 2, 18, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static struct rt2880_pmx_func pcie_rst_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static struct rt2880_pmx_func spi_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) FUNC("spi", 0, 34, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) FUNC("nand1", 2, 34, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static struct rt2880_pmx_func sdhci_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) FUNC("sdhci", 0, 41, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) FUNC("nand2", 2, 41, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static struct rt2880_pmx_group mt7621_pinmux_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) phys_addr_t mips_cpc_default_phys_base(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) panic("Cannot detect cpc address");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) void __init ralink_of_remap(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (!rt_sysc_membase || !rt_memc_membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) panic("Failed to remap core resources");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void soc_dev_init(struct ralink_soc_info *soc_info, u32 rev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct soc_device *soc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct soc_device_attribute *soc_dev_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (!soc_dev_attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) soc_dev_attr->soc_id = "mt7621";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) soc_dev_attr->family = "Ralink";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (((rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK) == 1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) (rev & CHIP_REV_ECO_MASK) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) soc_dev_attr->revision = "E2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) soc_dev_attr->revision = "E1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) soc_dev_attr->data = soc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) soc_dev = soc_device_register(soc_dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (IS_ERR(soc_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) kfree(soc_dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) void prom_soc_init(struct ralink_soc_info *soc_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned char *name = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 n0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 n1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Early detection of CMP support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) mips_cm_probe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) mips_cpc_probe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (mips_cps_numiocu(0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * mips_cm_probe() wipes out bootloader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * config for CM regions and we have to configure them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * again. This SoC cannot talk to pamlbus devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * witout proper iocu region set up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * FIXME: it would be better to do this with values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * from DT, but we need this very early because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * without this we cannot talk to pretty much anything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * including serial.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) write_gcr_reg0_base(MT7621_PALMBUS_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) CM_GCR_REGn_MASK_CMTGT_IOCU0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) __sync();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) name = "MT7621";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) soc_info->compatible = "mtk,mt7621-soc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ralink_soc = MT762X_SOC_MT7621AT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "MediaTek %s ver:%u eco:%u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) (rev & CHIP_REV_ECO_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) soc_info->mem_base = MT7621_DRAM_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) rt2880_pinmux_data = mt7621_pinmux_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) soc_dev_init(soc_info, rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (!register_cps_smp_ops())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (!register_cmp_smp_ops())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (!register_vsmp_smp_ops())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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