^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Parts of this file are based on Ralink's 2.6.21 BSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2013 John Crispin <john@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/mach-ralink/ralink_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/mach-ralink/mt7620.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/mach-ralink/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* analog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PMU0_CFG 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PMU_SW_SET BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define A_DCDC_EN BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define A_SSC_PERI BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define A_SSC_GEN BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define A_SSC_M 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define A_SSC_S 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define A_DLY_M 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define A_DLY_S 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define A_VTUNE_M 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* digital */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PMU1_CFG 0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DIG_SW_SEL BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* clock scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLKCFG_FDIV_MASK 0x1f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLKCFG_FDIV_USB_VAL 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLKCFG_FFRAC_MASK 0x001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLKCFG_FFRAC_USB_VAL 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* EFUSE bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define EFUSE_MT7688 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* DRAM type bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DRAM_TYPE_MT7628_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* does the board have sdram or ddram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int dram_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static struct rt2880_pmx_func mdio_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static struct rt2880_pmx_func uartf_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static struct rt2880_pmx_func wdt_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) FUNC("wdt rst", 0, 17, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) FUNC("wdt refclk", 0, 17, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static struct rt2880_pmx_func pcie_rst_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static struct rt2880_pmx_func nd_sd_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) FUNC("sd", MT7620_GPIO_MODE_SD, 47, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MT7620_GPIO_MODE_UART0_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MT7620_GPIO_MODE_MDIO_GPIO, MT7620_GPIO_MODE_MDIO_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static struct rt2880_pmx_func pwm1_grp_mt7628[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) FUNC("sdxc d6", 3, 19, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) FUNC("utif", 2, 19, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) FUNC("gpio", 1, 19, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) FUNC("pwm1", 0, 19, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static struct rt2880_pmx_func pwm0_grp_mt7628[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) FUNC("sdxc d7", 3, 18, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) FUNC("utif", 2, 18, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) FUNC("gpio", 1, 18, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) FUNC("pwm0", 0, 18, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static struct rt2880_pmx_func uart2_grp_mt7628[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) FUNC("sdxc d5 d4", 3, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) FUNC("pwm", 2, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) FUNC("gpio", 1, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) FUNC("uart2", 0, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static struct rt2880_pmx_func uart1_grp_mt7628[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) FUNC("sw_r", 3, 45, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) FUNC("pwm", 2, 45, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) FUNC("gpio", 1, 45, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) FUNC("uart1", 0, 45, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct rt2880_pmx_func i2c_grp_mt7628[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) FUNC("-", 3, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) FUNC("debug", 2, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) FUNC("gpio", 1, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) FUNC("i2c", 0, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("refclk", 0, 37, 1) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 36, 1) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 38, 1) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct rt2880_pmx_func sd_mode_grp_mt7628[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) FUNC("jtag", 3, 22, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) FUNC("utif", 2, 22, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) FUNC("gpio", 1, 22, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) FUNC("sdxc", 0, 22, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static struct rt2880_pmx_func uart0_grp_mt7628[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) FUNC("-", 3, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) FUNC("-", 2, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) FUNC("gpio", 1, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) FUNC("uart0", 0, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static struct rt2880_pmx_func i2s_grp_mt7628[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) FUNC("antenna", 3, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) FUNC("pcm", 2, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) FUNC("gpio", 1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) FUNC("i2s", 0, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static struct rt2880_pmx_func spi_cs1_grp_mt7628[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) FUNC("-", 3, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) FUNC("refclk", 2, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) FUNC("gpio", 1, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) FUNC("spi cs1", 0, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static struct rt2880_pmx_func spis_grp_mt7628[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) FUNC("pwm_uart2", 3, 14, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) FUNC("utif", 2, 14, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) FUNC("gpio", 1, 14, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) FUNC("spis", 0, 14, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static struct rt2880_pmx_func gpio_grp_mt7628[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) FUNC("pcie", 3, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) FUNC("refclk", 2, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) FUNC("gpio", 1, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) FUNC("gpio", 0, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static struct rt2880_pmx_func p4led_kn_grp_mt7628[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) FUNC("jtag", 3, 30, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) FUNC("utif", 2, 30, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) FUNC("gpio", 1, 30, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) FUNC("p4led_kn", 0, 30, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct rt2880_pmx_func p3led_kn_grp_mt7628[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) FUNC("jtag", 3, 31, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) FUNC("utif", 2, 31, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) FUNC("gpio", 1, 31, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) FUNC("p3led_kn", 0, 31, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static struct rt2880_pmx_func p2led_kn_grp_mt7628[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) FUNC("jtag", 3, 32, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) FUNC("utif", 2, 32, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) FUNC("gpio", 1, 32, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) FUNC("p2led_kn", 0, 32, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static struct rt2880_pmx_func p1led_kn_grp_mt7628[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) FUNC("jtag", 3, 33, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) FUNC("utif", 2, 33, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) FUNC("gpio", 1, 33, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) FUNC("p1led_kn", 0, 33, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static struct rt2880_pmx_func p0led_kn_grp_mt7628[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) FUNC("jtag", 3, 34, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) FUNC("rsvd", 2, 34, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) FUNC("gpio", 1, 34, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) FUNC("p0led_kn", 0, 34, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static struct rt2880_pmx_func wled_kn_grp_mt7628[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) FUNC("rsvd", 3, 35, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) FUNC("rsvd", 2, 35, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) FUNC("gpio", 1, 35, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) FUNC("wled_kn", 0, 35, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static struct rt2880_pmx_func p4led_an_grp_mt7628[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) FUNC("jtag", 3, 39, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) FUNC("utif", 2, 39, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) FUNC("gpio", 1, 39, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) FUNC("p4led_an", 0, 39, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static struct rt2880_pmx_func p3led_an_grp_mt7628[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) FUNC("jtag", 3, 40, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) FUNC("utif", 2, 40, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) FUNC("gpio", 1, 40, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) FUNC("p3led_an", 0, 40, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static struct rt2880_pmx_func p2led_an_grp_mt7628[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) FUNC("jtag", 3, 41, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) FUNC("utif", 2, 41, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) FUNC("gpio", 1, 41, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) FUNC("p2led_an", 0, 41, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static struct rt2880_pmx_func p1led_an_grp_mt7628[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) FUNC("jtag", 3, 42, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) FUNC("utif", 2, 42, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) FUNC("gpio", 1, 42, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) FUNC("p1led_an", 0, 42, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static struct rt2880_pmx_func p0led_an_grp_mt7628[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) FUNC("jtag", 3, 43, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) FUNC("rsvd", 2, 43, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) FUNC("gpio", 1, 43, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) FUNC("p0led_an", 0, 43, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static struct rt2880_pmx_func wled_an_grp_mt7628[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) FUNC("rsvd", 3, 44, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) FUNC("rsvd", 2, 44, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) FUNC("gpio", 1, 44, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) FUNC("wled_an", 0, 44, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define MT7628_GPIO_MODE_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define MT7628_GPIO_MODE_P4LED_KN 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define MT7628_GPIO_MODE_P3LED_KN 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define MT7628_GPIO_MODE_P2LED_KN 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define MT7628_GPIO_MODE_P1LED_KN 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define MT7628_GPIO_MODE_P0LED_KN 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define MT7628_GPIO_MODE_WLED_KN 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define MT7628_GPIO_MODE_P4LED_AN 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define MT7628_GPIO_MODE_P3LED_AN 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define MT7628_GPIO_MODE_P2LED_AN 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define MT7628_GPIO_MODE_P1LED_AN 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define MT7628_GPIO_MODE_P0LED_AN 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define MT7628_GPIO_MODE_WLED_AN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define MT7628_GPIO_MODE_PWM1 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define MT7628_GPIO_MODE_PWM0 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define MT7628_GPIO_MODE_UART2 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define MT7628_GPIO_MODE_UART1 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define MT7628_GPIO_MODE_I2C 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define MT7628_GPIO_MODE_REFCLK 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define MT7628_GPIO_MODE_PERST 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define MT7628_GPIO_MODE_WDT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define MT7628_GPIO_MODE_SPI 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define MT7628_GPIO_MODE_SDMODE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define MT7628_GPIO_MODE_UART0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define MT7628_GPIO_MODE_I2S 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define MT7628_GPIO_MODE_CS1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define MT7628_GPIO_MODE_SPIS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define MT7628_GPIO_MODE_GPIO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static struct rt2880_pmx_group mt7628an_pinmux_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) GRP_G("pwm1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 1, MT7628_GPIO_MODE_PWM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) GRP_G("pwm0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 1, MT7628_GPIO_MODE_PWM0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 1, MT7628_GPIO_MODE_UART2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) GRP_G("uart1", uart1_grp_mt7628, MT7628_GPIO_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 1, MT7628_GPIO_MODE_UART1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) GRP_G("i2c", i2c_grp_mt7628, MT7628_GPIO_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 1, MT7628_GPIO_MODE_I2C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) GRP("refclk", refclk_grp_mt7628, 1, MT7628_GPIO_MODE_REFCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) GRP("perst", perst_grp_mt7628, 1, MT7628_GPIO_MODE_PERST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) GRP("wdt", wdt_grp_mt7628, 1, MT7628_GPIO_MODE_WDT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) GRP("spi", spi_grp_mt7628, 1, MT7628_GPIO_MODE_SPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) GRP_G("sdmode", sd_mode_grp_mt7628, MT7628_GPIO_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 1, MT7628_GPIO_MODE_SDMODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) GRP_G("uart0", uart0_grp_mt7628, MT7628_GPIO_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 1, MT7628_GPIO_MODE_UART0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) GRP_G("i2s", i2s_grp_mt7628, MT7628_GPIO_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 1, MT7628_GPIO_MODE_I2S),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) GRP_G("spi cs1", spi_cs1_grp_mt7628, MT7628_GPIO_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 1, MT7628_GPIO_MODE_CS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) GRP_G("spis", spis_grp_mt7628, MT7628_GPIO_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 1, MT7628_GPIO_MODE_SPIS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 1, MT7628_GPIO_MODE_GPIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) GRP_G("wled_an", wled_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 1, MT7628_GPIO_MODE_WLED_AN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) GRP_G("p0led_an", p0led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 1, MT7628_GPIO_MODE_P0LED_AN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) GRP_G("p1led_an", p1led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 1, MT7628_GPIO_MODE_P1LED_AN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) GRP_G("p2led_an", p2led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 1, MT7628_GPIO_MODE_P2LED_AN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) GRP_G("p3led_an", p3led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 1, MT7628_GPIO_MODE_P3LED_AN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) GRP_G("p4led_an", p4led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 1, MT7628_GPIO_MODE_P4LED_AN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) GRP_G("wled_kn", wled_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 1, MT7628_GPIO_MODE_WLED_KN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) GRP_G("p0led_kn", p0led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 1, MT7628_GPIO_MODE_P0LED_KN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) GRP_G("p1led_kn", p1led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 1, MT7628_GPIO_MODE_P1LED_KN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) GRP_G("p2led_kn", p2led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 1, MT7628_GPIO_MODE_P2LED_KN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) GRP_G("p3led_kn", p3led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 1, MT7628_GPIO_MODE_P3LED_KN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) GRP_G("p4led_kn", p4led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 1, MT7628_GPIO_MODE_P4LED_KN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static inline int is_mt76x8(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return ralink_soc == MT762X_SOC_MT7628AN ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ralink_soc == MT762X_SOC_MT7688;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static __init u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u64 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) t = ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) t *= mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) do_div(t, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define MHZ(x) ((x) * 1000 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static __init unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) mt7620_get_xtal_rate(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (reg & SYSCFG0_XTAL_FREQ_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return MHZ(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return MHZ(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static __init unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) mt7620_get_periph_rate(unsigned long xtal_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (reg & CLKCFG0_PERI_CLK_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return xtal_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return MHZ(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static __init unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) mt7620_get_cpu_pll_rate(unsigned long xtal_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u32 mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (reg & CPLL_CFG0_BYPASS_REF_CLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return xtal_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if ((reg & CPLL_CFG0_SW_CFG) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return MHZ(600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) CPLL_CFG0_PLL_MULT_RATIO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) mul += 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (reg & CPLL_CFG0_LC_CURFCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) mul *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) CPLL_CFG0_PLL_DIV_RATIO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static __init unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (reg & CPLL_CFG1_CPU_AUX1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return xtal_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (reg & CPLL_CFG1_CPU_AUX0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return MHZ(480);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return cpu_pll_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static __init unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) mt7620_get_cpu_rate(unsigned long pll_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u32 mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) CPU_SYS_CLKCFG_CPU_FDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return mt7620_calc_rate(pll_rate, mul, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static const u32 mt7620_ocp_dividers[16] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static __init unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) mt7620_get_dram_rate(unsigned long pll_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return pll_rate / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return pll_rate / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static __init unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) mt7620_get_sys_rate(unsigned long cpu_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u32 ocp_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) CPU_SYS_CLKCFG_OCP_RATIO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return cpu_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) div = mt7620_ocp_dividers[ocp_ratio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return cpu_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return cpu_rate / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) void __init ralink_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) unsigned long xtal_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned long cpu_pll_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) unsigned long pll_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) unsigned long cpu_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) unsigned long sys_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) unsigned long dram_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) unsigned long periph_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) unsigned long pcmi2s_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) xtal_rate = mt7620_get_xtal_rate();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define RFMT(label) label ":%lu.%03luMHz "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define RINT(x) ((x) / 1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define RFRAC(x) (((x) / 1000) % 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (is_mt76x8()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (xtal_rate == MHZ(40))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) cpu_rate = MHZ(580);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) cpu_rate = MHZ(575);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dram_rate = sys_rate = cpu_rate / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) periph_rate = MHZ(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) pcmi2s_rate = MHZ(480);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ralink_clk_add("10000d00.uartlite", periph_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ralink_clk_add("10000e00.uartlite", periph_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) cpu_rate = mt7620_get_cpu_rate(pll_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) dram_rate = mt7620_get_dram_rate(pll_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) sys_rate = mt7620_get_sys_rate(cpu_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) periph_rate = mt7620_get_periph_rate(xtal_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) pcmi2s_rate = periph_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) RINT(xtal_rate), RFRAC(xtal_rate),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) RINT(pll_rate), RFRAC(pll_rate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ralink_clk_add("10000500.uart", periph_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) RINT(cpu_rate), RFRAC(cpu_rate),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) RINT(dram_rate), RFRAC(dram_rate),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) RINT(sys_rate), RFRAC(sys_rate),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) RINT(periph_rate), RFRAC(periph_rate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #undef RFRAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #undef RINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #undef RFMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ralink_clk_add("cpu", cpu_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ralink_clk_add("10000100.timer", periph_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ralink_clk_add("10000120.watchdog", periph_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ralink_clk_add("10000900.i2c", periph_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ralink_clk_add("10000a00.i2s", pcmi2s_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ralink_clk_add("10000b00.spi", sys_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ralink_clk_add("10000b40.spi", sys_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ralink_clk_add("10000c00.uartlite", periph_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ralink_clk_add("10000d00.uart1", periph_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ralink_clk_add("10000e00.uart2", periph_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ralink_clk_add("10180000.wmac", xtal_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * When the CPU goes into sleep mode, the BUS clock will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * too low for USB to function properly. Adjust the busses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * fractional divider to fix this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) void __init ralink_of_remap(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (!rt_sysc_membase || !rt_memc_membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) panic("Failed to remap core resources");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static __init void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) mt7620_dram_init(struct ralink_soc_info *soc_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) switch (dram_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) case SYSCFG0_DRAM_TYPE_SDRAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) pr_info("Board has SDRAM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) case SYSCFG0_DRAM_TYPE_DDR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) pr_info("Board has DDR1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) case SYSCFG0_DRAM_TYPE_DDR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) pr_info("Board has DDR2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static __init void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) mt7628_dram_init(struct ralink_soc_info *soc_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) switch (dram_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) case SYSCFG0_DRAM_TYPE_DDR1_MT7628:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) pr_info("Board has DDR1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) case SYSCFG0_DRAM_TYPE_DDR2_MT7628:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) pr_info("Board has DDR2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) void prom_soc_init(struct ralink_soc_info *soc_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) unsigned char *name = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u32 n0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u32 n1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u32 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u32 cfg0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u32 pmu0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u32 pmu1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) u32 bga;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (bga) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ralink_soc = MT762X_SOC_MT7620A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) name = "MT7620A";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) soc_info->compatible = "ralink,mt7620a-soc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ralink_soc = MT762X_SOC_MT7620N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) name = "MT7620N";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) soc_info->compatible = "ralink,mt7620n-soc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (efuse & EFUSE_MT7688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ralink_soc = MT762X_SOC_MT7688;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) name = "MT7688";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ralink_soc = MT762X_SOC_MT7628AN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) name = "MT7628AN";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) soc_info->compatible = "ralink,mt7628an-soc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) "MediaTek %s ver:%u eco:%u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) (rev & CHIP_REV_ECO_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (is_mt76x8()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) dram_type = cfg0 & DRAM_TYPE_MT7628_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) SYSCFG0_DRAM_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (dram_type == SYSCFG0_DRAM_TYPE_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) dram_type = SYSCFG0_DRAM_TYPE_SDRAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) soc_info->mem_base = MT7620_DRAM_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (is_mt76x8())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) mt7628_dram_init(soc_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) mt7620_dram_init(soc_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) pmu0 = __raw_readl(sysc + PMU0_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) pmu1 = __raw_readl(sysc + PMU1_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) pr_info("Analog PMU set to %s control\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) pr_info("Digital PMU set to %s control\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (is_mt76x8())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) rt2880_pinmux_data = mt7628an_pinmux_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) rt2880_pinmux_data = mt7620a_pinmux_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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