^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 John Crispin <john@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/irq_cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define INTC_INT_GLOBAL BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RALINK_CPU_IRQ_PCI (MIPS_CPU_IRQ_BASE + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RALINK_CPU_IRQ_FE (MIPS_CPU_IRQ_BASE + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RALINK_CPU_IRQ_WIFI (MIPS_CPU_IRQ_BASE + 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RALINK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* we have a cascade of 8 irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RALINK_INTC_IRQ_BASE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* we have 32 SoC irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RALINK_INTC_IRQ_COUNT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RALINK_INTC_IRQ_PERFC (RALINK_INTC_IRQ_BASE + 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) enum rt_intc_regs_enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) INTC_REG_STATUS0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) INTC_REG_STATUS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) INTC_REG_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) INTC_REG_RAW_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) INTC_REG_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) INTC_REG_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static u32 rt_intc_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) [INTC_REG_STATUS0] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) [INTC_REG_STATUS1] = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) [INTC_REG_TYPE] = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) [INTC_REG_RAW_STATUS] = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) [INTC_REG_ENABLE] = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) [INTC_REG_DISABLE] = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static void __iomem *rt_intc_membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int rt_perfcount_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static inline void rt_intc_w32(u32 val, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __raw_writel(val, rt_intc_membase + rt_intc_regs[reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static inline u32 rt_intc_r32(unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return __raw_readl(rt_intc_membase + rt_intc_regs[reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static void ralink_intc_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) rt_intc_w32(BIT(d->hwirq), INTC_REG_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static void ralink_intc_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) rt_intc_w32(BIT(d->hwirq), INTC_REG_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static struct irq_chip ralink_intc_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .name = "INTC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .irq_unmask = ralink_intc_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .irq_mask = ralink_intc_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .irq_mask_ack = ralink_intc_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int get_c0_perfcount_int(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return rt_perfcount_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int get_c0_compare_int(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return CP0_LEGACY_COMPARE_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static void ralink_intc_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 pending = rt_intc_r32(INTC_REG_STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct irq_domain *domain = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) spurious_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) asmlinkage void plat_irq_dispatch(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned long pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pending = read_c0_status() & read_c0_cause() & ST0_IM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (pending & STATUSF_IP7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) do_IRQ(RALINK_CPU_IRQ_COUNTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) else if (pending & STATUSF_IP5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) do_IRQ(RALINK_CPU_IRQ_FE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) else if (pending & STATUSF_IP6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) do_IRQ(RALINK_CPU_IRQ_WIFI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) else if (pending & STATUSF_IP4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) do_IRQ(RALINK_CPU_IRQ_PCI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) else if (pending & STATUSF_IP2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) do_IRQ(RALINK_CPU_IRQ_INTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) spurious_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) irq_set_chip_and_handler(irq, &ralink_intc_irq_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const struct irq_domain_ops irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .xlate = irq_domain_xlate_onecell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .map = intc_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int __init intc_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (!of_property_read_u32_array(node, "ralink,intc-registers",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) rt_intc_regs, 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pr_info("intc: using register map from devicetree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (!irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) panic("Failed to get INTC IRQ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (of_address_to_resource(node, 0, &res))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) panic("Failed to get intc memory range");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (!request_mem_region(res.start, resource_size(&res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) res.name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) pr_err("Failed to request intc memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) rt_intc_membase = ioremap(res.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (!rt_intc_membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) panic("Failed to remap intc memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) rt_intc_w32(~0, INTC_REG_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* route all INTC interrupts to MIPS HW0 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) rt_intc_w32(0, INTC_REG_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) domain = irq_domain_add_legacy(node, RALINK_INTC_IRQ_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) RALINK_INTC_IRQ_BASE, 0, &irq_domain_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (!domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) panic("Failed to add irqdomain");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) rt_intc_w32(INTC_INT_GLOBAL, INTC_REG_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) irq_set_chained_handler_and_data(irq, ralink_intc_irq_handler, domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* tell the kernel which irq is used for performance monitoring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) rt_perfcount_irq = irq_create_mapping(domain, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static struct of_device_id __initdata of_irq_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { .compatible = "ralink,rt2880-intc", .data = intc_of_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) void __init arch_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) of_irq_init(of_irq_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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