Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *  Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/serial_reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/addrspace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifdef CONFIG_SOC_RT288X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define EARLY_UART_BASE		0x300c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CHIPID_BASE		0x300004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #elif defined(CONFIG_SOC_MT7621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define EARLY_UART_BASE		0x1E000c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CHIPID_BASE		0x1E000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define EARLY_UART_BASE		0x10000c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CHIPID_BASE		0x10000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MT7628_CHIP_NAME1	0x20203832
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define UART_REG_TX		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define UART_REG_LCR		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define UART_REG_LSR		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define UART_REG_LSR_RT2880	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static __iomem void *uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static __iomem void *chipid_membase = (__iomem void *) KSEG1ADDR(CHIPID_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int init_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static inline void uart_w32(u32 val, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	__raw_writel(val, uart_membase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static inline u32 uart_r32(unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	return __raw_readl(uart_membase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static inline int soc_is_mt7628(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	return IS_ENABLED(CONFIG_SOC_MT7620) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		(__raw_readl(chipid_membase) == MT7628_CHIP_NAME1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void find_uart_base(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	if (!soc_is_mt7628())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		u32 reg = uart_r32(UART_REG_LCR + (0x100 * i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		if (!reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 							  (0x100 * i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void prom_putchar(char ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	if (!init_complete) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 		find_uart_base();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 		init_complete = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 		uart_w32((unsigned char)ch, UART_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 		while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 			;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 		while ((uart_r32(UART_REG_LSR_RT2880) & UART_LSR_THRE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 			;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 		uart_w32((unsigned char)ch, UART_REG_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 		while ((uart_r32(UART_REG_LSR_RT2880) & UART_LSR_THRE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 			;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }