Orange Pi5 kernel

Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards

3 Commits   0 Branches   0 Tags   |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2011 Wind River Systems,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *   written by Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/cpu-info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) unsigned long PCIBIOS_MIN_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) EXPORT_SYMBOL(PCIBIOS_MIN_IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned long PCIBIOS_MIN_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static int __init pcibios_set_cache_line_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	unsigned int lsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	 * Set PCI cacheline size to that of the highest level in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	 * cache hierarchy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	lsize = cpu_dcache_line_size();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	lsize = cpu_scache_line_size() ? : lsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	lsize = cpu_tcache_line_size() ? : lsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	BUG_ON(!lsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	pci_dfl_cache_line_size = lsize >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) arch_initcall(pcibios_set_cache_line_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) void pci_resource_to_user(const struct pci_dev *dev, int bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 			  const struct resource *rsrc, resource_size_t *start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 			  resource_size_t *end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	phys_addr_t size = resource_size(rsrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	*start = fixup_bigphys_addr(rsrc->start, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	*end = rsrc->start + size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }