^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2003 Christoph Hellwig (hch@lst.de)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dma-direct.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_data/xtalk-bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/nvmem-consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/crc16.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/pci/bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/paccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/sn/irq_alloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/sn/ioc3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CRC16_INIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CRC16_VALID 0xb001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Common phys<->dma mapping for platforms using pci xtalk bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct pci_dev *pdev = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct bridge_controller *bc = BRIDGE_CONTROLLER(pdev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return bc->baddr + paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dma_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return dma_addr & ~(0xffUL << 56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Most of the IOC3 PCI config register aren't present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * we emulate what is needed for a normal PCI enumeration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static int ioc3_cfg_rd(void *addr, int where, int size, u32 *value, u32 sid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 cf, shift, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) switch (where & ~3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) case 0x00 ... 0x10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) case 0x40 ... 0x44:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (get_dbe(cf, (u32 *)addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) case 0x2c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) cf = sid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) case 0x3c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* emulate sane interrupt pin value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) cf = 0x00000100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) cf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) shift = (where & 3) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) mask = 0xffffffffU >> ((4 - size) << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *value = (cf >> shift) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int ioc3_cfg_wr(void *addr, int where, int size, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 cf, shift, mask, smask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (get_dbe(cf, (u32 *)addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) shift = ((where & 3) << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) mask = (0xffffffffU >> ((4 - size) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) smask = mask << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) cf = (cf & ~smask) | ((value & mask) << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (put_dbe(cf, (u32 *)addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static void bridge_disable_swapping(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int slot = PCI_SLOT(dev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Turn off byte swapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) bridge_clr(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) bridge_read(bc, b_widget.w_tflush); /* Flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) bridge_disable_swapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * not really documented, so right now I can't write code which uses it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * Therefore we use type 0 accesses for now even though they won't work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * correctly for PCI-to-PCI bridges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * The function is complicated by the ultimate brokenness of the IOC3 chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * which is used in SGI systems. The IOC3 can only handle 32-bit PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * accesses and does only decode parts of it's address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int where, int size, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct bridge_regs *bridge = bc->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int slot = PCI_SLOT(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int fn = PCI_FUNC(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (get_dbe(cf, (u32 *)addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * IOC3 is broken beyond belief ... Don't even give the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * generic PCI code a chance to look at it for real ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return ioc3_cfg_rd(addr, where, size, value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) bc->ioc3_sid[slot]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) res = get_dbe(*value, (u8 *)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) res = get_dbe(*value, (u16 *)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) res = get_dbe(*value, (u32 *)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int where, int size, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct bridge_regs *bridge = bc->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int busno = bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int slot = PCI_SLOT(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int fn = PCI_FUNC(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) void *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (get_dbe(cf, (u32 *)addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * IOC3 is broken beyond belief ... Don't even give the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * generic PCI code a chance to look at it for real ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) addr = &bridge->b_type1_cfg.c[(fn << 8) | (where & ~3)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return ioc3_cfg_rd(addr, where, size, value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) bc->ioc3_sid[slot]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) res = get_dbe(*value, (u8 *)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) res = get_dbe(*value, (u16 *)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) res = get_dbe(*value, (u32 *)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int pci_read_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int where, int size, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (!pci_is_root_bus(bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return pci_conf1_read_config(bus, devfn, where, size, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return pci_conf0_read_config(bus, devfn, where, size, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int where, int size, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct bridge_regs *bridge = bc->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int slot = PCI_SLOT(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int fn = PCI_FUNC(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) void *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (get_dbe(cf, (u32 *)addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * IOC3 is broken beyond belief ... Don't even give the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * generic PCI code a chance to look at it for real ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return ioc3_cfg_wr(addr, where, size, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) res = put_dbe(value, (u8 *)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) res = put_dbe(value, (u16 *)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) res = put_dbe(value, (u32 *)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int where, int size, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct bridge_regs *bridge = bc->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int slot = PCI_SLOT(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int fn = PCI_FUNC(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int busno = bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) void *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (get_dbe(cf, (u32 *)addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * IOC3 is broken beyond belief ... Don't even give the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * generic PCI code a chance to look at it for real ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return ioc3_cfg_wr(addr, where, size, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) res = put_dbe(value, (u8 *)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) res = put_dbe(value, (u16 *)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) res = put_dbe(value, (u32 *)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int pci_write_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int where, int size, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (!pci_is_root_bus(bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return pci_conf1_write_config(bus, devfn, where, size, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return pci_conf0_write_config(bus, devfn, where, size, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static struct pci_ops bridge_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .read = pci_read_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .write = pci_write_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct bridge_irq_chip_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct bridge_controller *bc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) nasid_t nasid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int bridge_set_affinity(struct irq_data *d, const struct cpumask *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #ifdef CONFIG_NUMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct bridge_irq_chip_data *data = d->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int bit = d->parent_data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int pin = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int ret, cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ret = irq_chip_set_affinity_parent(d, mask, force);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) cpu = cpumask_first_and(mask, cpu_online_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) data->nasid = cpu_to_node(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) bridge_write(data->bc, b_int_addr[pin].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) (((data->bc->intr_addr >> 30) & 0x30000) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) bit | (data->nasid << 8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) bridge_read(data->bc, b_wid_tflush);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return irq_chip_set_affinity_parent(d, mask, force);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct irq_chip bridge_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .name = "BRIDGE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .irq_mask = irq_chip_mask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .irq_unmask = irq_chip_unmask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .irq_set_affinity = bridge_set_affinity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int bridge_domain_alloc(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned int nr_irqs, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct bridge_irq_chip_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct irq_alloc_info *info = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (nr_irqs > 1 || !info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) data = kzalloc(sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) data->bc = info->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) data->nasid = info->nasid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) irq_domain_set_info(domain, virq, info->pin, &bridge_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) data, handle_level_irq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static void bridge_domain_free(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct irq_data *irqd = irq_domain_get_irq_data(domain, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) kfree(irqd->chip_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) irq_domain_free_irqs_top(domain, virq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static int bridge_domain_activate(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct irq_data *irqd, bool reserve)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct bridge_irq_chip_data *data = irqd->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct bridge_controller *bc = data->bc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int bit = irqd->parent_data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int pin = irqd->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u32 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) bridge_write(bc, b_int_addr[pin].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) (((bc->intr_addr >> 30) & 0x30000) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) bit | (data->nasid << 8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) bridge_set(bc, b_int_enable, (1 << pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) bridge_set(bc, b_int_enable, 0x7ffffe00); /* more stuff in int_enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * Enable sending of an interrupt clear packt to the hub on a high to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * low transition of the interrupt pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * IRIX sets additional bits in the address which are documented as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * reserved in the bridge docs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) bridge_set(bc, b_int_mode, (1UL << pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * We assume the bridge to have a 1:1 mapping between devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * (slots) and intr pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) device = bridge_read(bc, b_int_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) device &= ~(7 << (pin*3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) device |= (pin << (pin*3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) bridge_write(bc, b_int_device, device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) bridge_read(bc, b_wid_tflush);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static void bridge_domain_deactivate(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct irq_data *irqd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct bridge_irq_chip_data *data = irqd->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) bridge_clr(data->bc, b_int_enable, (1 << irqd->hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) bridge_read(data->bc, b_wid_tflush);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static const struct irq_domain_ops bridge_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .alloc = bridge_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .free = bridge_domain_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .activate = bridge_domain_activate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .deactivate = bridge_domain_deactivate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * All observed requests have pin == 1. We could have a global here, that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * gets incremented and returned every time - unfortunately, pci_map_irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * may be called on the same device over and over, and need to return the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * A given PCI device, in general, should be able to intr any of the cpus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * on any one of the hubs connected to its xbow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static int bridge_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct irq_alloc_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) switch (pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) case PCI_INTERRUPT_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case PCI_INTERRUPT_INTA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) case PCI_INTERRUPT_INTC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) pin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) case PCI_INTERRUPT_INTB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) case PCI_INTERRUPT_INTD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) pin = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) irq = bc->pci_int[slot][pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (irq == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) info.ctrl = bc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) info.nasid = bc->nasid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) info.pin = bc->int_mapping[slot][pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) irq = irq_domain_alloc_irqs(bc->domain, 1, bc->nasid, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) bc->pci_int[slot][pin] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define IOC3_SID(sid) (PCI_VENDOR_ID_SGI | ((sid) << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static void bridge_setup_ip27_baseio6g(struct bridge_controller *bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP27_BASEIO6G);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) bc->ioc3_sid[6] = IOC3_SID(IOC3_SUBSYS_IP27_MIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) bc->int_mapping[2][1] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) bc->int_mapping[6][1] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static void bridge_setup_ip27_baseio(struct bridge_controller *bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP27_BASEIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) bc->int_mapping[2][1] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static void bridge_setup_ip29_baseio(struct bridge_controller *bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP29_SYSBOARD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) bc->int_mapping[2][1] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static void bridge_setup_ip30_sysboard(struct bridge_controller *bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP30_SYSBOARD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) bc->int_mapping[2][1] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static void bridge_setup_menet(struct bridge_controller *bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) bc->ioc3_sid[0] = IOC3_SID(IOC3_SUBSYS_MENET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) bc->ioc3_sid[1] = IOC3_SID(IOC3_SUBSYS_MENET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_MENET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) bc->ioc3_sid[3] = IOC3_SID(IOC3_SUBSYS_MENET4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static void bridge_setup_io7(struct bridge_controller *bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) bc->ioc3_sid[4] = IOC3_SID(IOC3_SUBSYS_IO7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static void bridge_setup_io8(struct bridge_controller *bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) bc->ioc3_sid[4] = IOC3_SID(IOC3_SUBSYS_IO8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static void bridge_setup_io9(struct bridge_controller *bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) bc->ioc3_sid[1] = IOC3_SID(IOC3_SUBSYS_IO9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static void bridge_setup_ip34_fuel_sysboard(struct bridge_controller *bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) bc->ioc3_sid[4] = IOC3_SID(IOC3_SUBSYS_IP34_SYSBOARD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define BRIDGE_BOARD_SETUP(_partno, _setup) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) { .match = _partno, .setup = _setup }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) char *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) void (*setup)(struct bridge_controller *bc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) } bridge_ioc3_devid[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) BRIDGE_BOARD_SETUP("030-0734-", bridge_setup_ip27_baseio6g),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) BRIDGE_BOARD_SETUP("030-0880-", bridge_setup_ip27_baseio6g),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) BRIDGE_BOARD_SETUP("030-1023-", bridge_setup_ip27_baseio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) BRIDGE_BOARD_SETUP("030-1124-", bridge_setup_ip27_baseio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) BRIDGE_BOARD_SETUP("030-1025-", bridge_setup_ip29_baseio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) BRIDGE_BOARD_SETUP("030-1244-", bridge_setup_ip29_baseio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) BRIDGE_BOARD_SETUP("030-1389-", bridge_setup_ip29_baseio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) BRIDGE_BOARD_SETUP("030-0887-", bridge_setup_ip30_sysboard),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) BRIDGE_BOARD_SETUP("030-1467-", bridge_setup_ip30_sysboard),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) BRIDGE_BOARD_SETUP("030-0873-", bridge_setup_menet),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) BRIDGE_BOARD_SETUP("030-1557-", bridge_setup_io7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) BRIDGE_BOARD_SETUP("030-1673-", bridge_setup_io8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) BRIDGE_BOARD_SETUP("030-1771-", bridge_setup_io9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) BRIDGE_BOARD_SETUP("030-1707-", bridge_setup_ip34_fuel_sysboard),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static void bridge_setup_board(struct bridge_controller *bc, char *partnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) for (i = 0; i < ARRAY_SIZE(bridge_ioc3_devid); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (!strncmp(partnum, bridge_ioc3_devid[i].match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) strlen(bridge_ioc3_devid[i].match))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) bridge_ioc3_devid[i].setup(bc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static int bridge_nvmem_match(struct device *dev, const void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) const char *name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) const char *prefix = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (strlen(name) < strlen(prefix))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return memcmp(prefix, dev_name(dev), strlen(prefix)) == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static int bridge_get_partnum(u64 baddr, char *partnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct nvmem_device *nvmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) char prefix[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) u8 prom[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) snprintf(prefix, sizeof(prefix), "bridge-%012llx-0b-", baddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) nvmem = nvmem_device_find(prefix, bridge_nvmem_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (IS_ERR(nvmem))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return PTR_ERR(nvmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ret = nvmem_device_read(nvmem, 0, 64, prom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) nvmem_device_put(nvmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (ret != 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (crc16(CRC16_INIT, prom, 32) != CRC16_VALID ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) crc16(CRC16_INIT, prom + 32, 32) != CRC16_VALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* Assemble part number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) for (i = 0; i < 19; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (prom[i + 11] != ' ')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) partnum[j++] = prom[i + 11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) for (i = 0; i < 6; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (prom[i + 32] != ' ')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) partnum[j++] = prom[i + 32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) partnum[j] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static int bridge_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct xtalk_bridge_platform_data *bd = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct bridge_controller *bc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct pci_host_bridge *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct irq_domain *domain, *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct fwnode_handle *fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) char partnum[26];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) int slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* get part number from one wire prom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (bridge_get_partnum(virt_to_phys((void *)bd->bridge_addr), partnum))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return -EPROBE_DEFER; /* not available yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) parent = irq_get_default_host();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (!parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) fn = irq_domain_alloc_named_fwnode("BRIDGE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (!fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) domain = irq_domain_create_hierarchy(parent, 0, 8, fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) &bridge_domain_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (!domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) irq_domain_free_fwnode(fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) pci_set_flags(PCI_PROBE_ONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) host = devm_pci_alloc_host_bridge(dev, sizeof(*bc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (!host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) goto err_remove_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) bc = pci_host_bridge_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) bc->busn.name = "Bridge PCI busn";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) bc->busn.start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) bc->busn.end = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) bc->busn.flags = IORESOURCE_BUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) bc->domain = domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) pci_add_resource_offset(&host->windows, &bd->mem, bd->mem_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) pci_add_resource_offset(&host->windows, &bd->io, bd->io_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) pci_add_resource(&host->windows, &bc->busn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) err = devm_request_pci_bus_resources(dev, &host->windows);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) goto err_free_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) bc->nasid = bd->nasid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) bc->baddr = (u64)bd->masterwid << 60 | PCI64_ATTR_BAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) bc->base = (struct bridge_regs *)bd->bridge_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) bc->intr_addr = bd->intr_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * Clear all pending interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) bridge_write(bc, b_int_rst_stat, BRIDGE_IRR_ALL_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * Until otherwise set up, assume all interrupts are from slot 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) bridge_write(bc, b_int_device, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * disable swapping for big windows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) bridge_clr(bc, b_wid_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) BRIDGE_CTRL_IO_SWAP | BRIDGE_CTRL_MEM_SWAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #ifdef CONFIG_PAGE_SIZE_4KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) bridge_clr(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #else /* 16kB or larger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) bridge_set(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * Hmm... IRIX sets additional bits in the address which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * are documented as reserved in the bridge docs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) bridge_write(bc, b_wid_int_upper,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ((bc->intr_addr >> 32) & 0xffff) | (bd->masterwid << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) bridge_write(bc, b_wid_int_lower, bc->intr_addr & 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) bridge_write(bc, b_dir_map, (bd->masterwid << 20)); /* DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) bridge_write(bc, b_int_enable, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) for (slot = 0; slot < 8; slot++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) bridge_set(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) bc->pci_int[slot][0] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) bc->pci_int[slot][1] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* default interrupt pin mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) bc->int_mapping[slot][0] = slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) bc->int_mapping[slot][1] = slot ^ 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) bridge_read(bc, b_wid_tflush); /* wait until Bridge PIO complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) bridge_setup_board(bc, partnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) host->dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) host->sysdata = bc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) host->busnr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) host->ops = &bridge_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) host->map_irq = bridge_map_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) host->swizzle_irq = pci_common_swizzle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) err = pci_scan_root_bus_bridge(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) goto err_free_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) pci_bus_claim_resources(host->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) pci_bus_add_devices(host->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) platform_set_drvdata(pdev, host->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) err_free_resource:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) pci_free_resource_list(&host->windows);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) err_remove_domain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) irq_domain_remove(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) irq_domain_free_fwnode(fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static int bridge_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct pci_bus *bus = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct fwnode_handle *fn = bc->domain->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) irq_domain_remove(bc->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) irq_domain_free_fwnode(fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) pci_lock_rescan_remove();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) pci_stop_root_bus(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) pci_remove_root_bus(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) pci_unlock_rescan_remove();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static struct platform_driver bridge_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .probe = bridge_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .remove = bridge_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .name = "xtalk-bridge",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) builtin_platform_driver(bridge_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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