^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This software is available to you under a choice of one of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * licenses. You may choose to be licensed under the terms of the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * General Public License (GPL) Version 2, available from the file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * COPYING in the main directory of this source tree, or the NetLogic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * license below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * notice, this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * 2. Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * notice, this list of conditions and the following disclaimer in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * the documentation and/or other materials provided with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/irqdesc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/pci_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <asm/netlogic/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <asm/netlogic/haldefs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <asm/netlogic/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <asm/netlogic/xlr/msidef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <asm/netlogic/xlr/iomap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <asm/netlogic/xlr/pic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <asm/netlogic/xlr/xlr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static void *pci_config_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define pci_cfg_addr(bus, devfn, off) (((bus) << 16) | ((devfn) << 8) | (off))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* PCI ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 *cfgaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) cfgaddr = (u32 *)(pci_config_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) pci_cfg_addr(bus->number, devfn, where & ~3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) data = *cfgaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return cpu_to_le32(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int where, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 *cfgaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) cfgaddr = (u32 *)(pci_config_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) pci_cfg_addr(bus->number, devfn, where & ~3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *cfgaddr = cpu_to_le32(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if ((size == 2) && (where & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) else if ((size == 4) && (where & 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) data = pci_cfg_read_32bit(bus, devfn, where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *val = (data >> ((where & 3) << 3)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) *val = (data >> ((where & 3) << 3)) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *val = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if ((size == 2) && (where & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) else if ((size == 4) && (where & 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) data = pci_cfg_read_32bit(bus, devfn, where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) data = (data & ~(0xff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) (val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) data = (data & ~(0xffff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) (val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pci_cfg_write_32bit(bus, devfn, where, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct pci_ops nlm_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .read = nlm_pcibios_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .write = nlm_pcibios_write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct resource nlm_pci_mem_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .name = "XLR PCI MEM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .end = 0xdfffffffUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static struct resource nlm_pci_io_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .name = "XLR IO MEM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .start = 0x10000000UL, /* 16MB PCI IO @ 0x1000_0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .end = 0x100fffffUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct pci_controller nlm_pci_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .pci_ops = &nlm_pci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .mem_resource = &nlm_pci_mem_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .mem_offset = 0x00000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .io_resource = &nlm_pci_io_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .io_offset = 0x00000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * The top level PCIe links on the XLS PCIe controller appear as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * bridges. Given a device, this function finds which link it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct pci_dev *xls_get_pcie_link(const struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct pci_bus *bus, *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Find the bridge on bus 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) bus = dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) for (p = bus->parent; p && p->number != 0; p = p->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) bus = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return p ? bus->self : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int nlm_pci_link_to_irq(int link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) switch (link) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return PIC_PCIE_LINK0_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return PIC_PCIE_LINK1_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (nlm_chip_is_xls_b())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return PIC_PCIE_XLSB0_LINK2_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return PIC_PCIE_LINK2_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (nlm_chip_is_xls_b())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return PIC_PCIE_XLSB0_LINK3_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return PIC_PCIE_LINK3_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) WARN(1, "Unexpected link %d\n", link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int get_irq_vector(const struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct pci_dev *lnk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (!nlm_chip_is_xls())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return PIC_PCIX_IRQ; /* for XLR just one IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) lnk = xls_get_pcie_link(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (lnk == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) link = PCI_SLOT(lnk->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return nlm_pci_link_to_irq(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) void arch_teardown_msi_irq(unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct msi_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct pci_dev *lnk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* MSI not supported on XLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (!nlm_chip_is_xls())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * Enable MSI on the XLS PCIe controller bridge which was disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * at enumeration, the bridge MSI capability is at 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) lnk = xls_get_pcie_link(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (lnk == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pci_read_config_word(lnk, 0x50 + PCI_MSI_FLAGS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if ((val & PCI_MSI_FLAGS_ENABLE) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) val |= PCI_MSI_FLAGS_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) pci_write_config_word(lnk, 0x50 + PCI_MSI_FLAGS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) irq = get_irq_vector(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) msg.address_hi = MSI_ADDR_BASE_HI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) msg.address_lo = MSI_ADDR_BASE_LO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MSI_ADDR_DEST_MODE_PHYSICAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) MSI_ADDR_REDIRECTION_CPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) msg.data = MSI_DATA_TRIGGER_EDGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MSI_DATA_LEVEL_ASSERT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MSI_DATA_DELIVERY_FIXED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret = irq_set_msi_desc(irq, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) pci_write_msi_msg(irq, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Extra ACK needed for XLR on chip PCI controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static void xlr_pci_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) uint64_t pcibase = nlm_mmio_base(NETLOGIC_IO_PCIX_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) nlm_read_reg(pcibase, (0x140 >> 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Extra ACK needed for XLS on chip PCIe controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static void xls_pcie_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) uint64_t pciebase_le = nlm_mmio_base(NETLOGIC_IO_PCIE_1_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) switch (d->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) case PIC_PCIE_LINK0_IRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case PIC_PCIE_LINK1_IRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case PIC_PCIE_LINK2_IRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) case PIC_PCIE_LINK3_IRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* For XLS B silicon, the 3,4 PCI interrupts are different */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static void xls_pcie_ack_b(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) uint64_t pciebase_le = nlm_mmio_base(NETLOGIC_IO_PCIE_1_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) switch (d->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) case PIC_PCIE_LINK0_IRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) case PIC_PCIE_LINK1_IRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case PIC_PCIE_XLSB0_LINK2_IRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) case PIC_PCIE_XLSB0_LINK3_IRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return get_irq_vector(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* Do platform specific device initialization at pci_enable_device() time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int pcibios_plat_dev_init(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int __init pcibios_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) void (*extra_ack)(struct irq_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int link, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* PSB assigns PCI resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) pci_set_flags(PCI_PROBE_ONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Extend IO port for memory mapped io */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ioport_resource.start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ioport_resource.end = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) set_io_port_base(CKSEG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) nlm_pci_controller.io_map_base = CKSEG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) pr_info("Registering XLR/XLS PCIX/PCIE Controller.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) register_pci_controller(&nlm_pci_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * For PCI interrupts, we need to ack the PCI controller too, overload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * irq handler data to do this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (!nlm_chip_is_xls()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* XLR PCI controller ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) nlm_set_pic_extra_ack(0, PIC_PCIX_IRQ, xlr_pci_ack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (nlm_chip_is_xls_b())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) extra_ack = xls_pcie_ack_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) extra_ack = xls_pcie_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) for (link = 0; link < 4; link++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) irq = nlm_pci_link_to_irq(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) nlm_set_pic_extra_ack(0, irq, extra_ack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) arch_initcall(pcibios_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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