Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright (c) 2003-2012 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * This software is available to you under a choice of one of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * licenses.  You may choose to be licensed under the terms of the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * General Public License (GPL) Version 2, available from the file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * COPYING in the main directory of this source tree, or the Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * license below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * modification, are permitted provided that the following conditions
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *    notice, this list of conditions and the following disclaimer.
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *    notice, this list of conditions and the following disclaimer in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *    the documentation and/or other materials provided with the
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #include <linux/irqdesc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #include <asm/netlogic/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #include <asm/netlogic/haldefs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #include <asm/netlogic/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #include <asm/netlogic/mips-extns.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #include <asm/netlogic/xlp-hal/iomap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #include <asm/netlogic/xlp-hal/xlp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #include <asm/netlogic/xlp-hal/pic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #include <asm/netlogic/xlp-hal/pcibus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #include <asm/netlogic/xlp-hal/bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static void *pci_config_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define pci_cfg_addr(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) /* PCI ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	u32 *cfgaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	where &= ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	if (cpu_is_xlp9xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		/* be very careful on SoC buses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		if (bus->number == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 			/* Scan only existing nodes - uboot bug? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			if (PCI_SLOT(devfn) != 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 					   !nlm_node_present(PCI_FUNC(devfn)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 				return 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		} else if (bus->parent->number == 0) {	/* SoC bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			if (PCI_SLOT(devfn) == 0)	/* b.0.0 hangs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 				return 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 			if (devfn == 44)		/* b.5.4 hangs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 				return 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	} else if (bus->number == 0 && PCI_SLOT(devfn) == 1 && where == 0x954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		return 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	cfgaddr = (u32 *)(pci_config_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			pci_cfg_addr(bus->number, devfn, where));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	data = *cfgaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	int where, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	u32 *cfgaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	cfgaddr = (u32 *)(pci_config_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			pci_cfg_addr(bus->number, devfn, where & ~3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	*cfgaddr = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	if ((size == 2) && (where & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	else if ((size == 4) && (where & 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	data = pci_cfg_read_32bit(bus, devfn, where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		*val = (data >> ((where & 3) << 3)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		*val = (data >> ((where & 3) << 3)) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		*val = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if ((size == 2) && (where & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	else if ((size == 4) && (where & 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	data = pci_cfg_read_32bit(bus, devfn, where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		data = (data & ~(0xff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			(val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		data = (data & ~(0xffff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			(val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	pci_cfg_write_32bit(bus, devfn, where, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct pci_ops nlm_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.read  = nlm_pcibios_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.write = nlm_pcibios_write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct resource nlm_pci_mem_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.name		= "XLP PCI MEM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.start		= 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.end		= 0xdfffffffUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.flags		= IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static struct resource nlm_pci_io_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.name		= "XLP IO MEM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.start		= 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.end		= 0x17ffffffUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.flags		= IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct pci_controller nlm_pci_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	.index		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.pci_ops	= &nlm_pci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.mem_resource	= &nlm_pci_mem_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.mem_offset	= 0x00000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.io_resource	= &nlm_pci_io_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.io_offset	= 0x00000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct pci_bus *bus, *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	bus = dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (cpu_is_xlp9xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		/* find bus with grand parent number == 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		for (p = bus->parent; p && p->parent && p->parent->number != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 				p = p->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			bus = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		return (p && p->parent) ? bus->self : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		/* Find the bridge on bus 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		for (p = bus->parent; p && p->number != 0; p = p->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			bus = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		return p ? bus->self : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int xlp_socdev_to_node(const struct pci_dev *lnkdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (cpu_is_xlp9xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		return PCI_FUNC(lnkdev->bus->self->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return PCI_SLOT(lnkdev->devfn) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct pci_dev *lnkdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	int lnkfunc, node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	 * For XLP PCIe, there is an IRQ per Link, find out which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	 * link the device is on to assign interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	lnkdev = xlp_get_pcie_link(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	if (lnkdev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	lnkfunc = PCI_FUNC(lnkdev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	node = xlp_socdev_to_node(lnkdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	return nlm_irq_to_xirq(node, PIC_PCIE_LINK_LEGACY_IRQ(lnkfunc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Do platform specific device initialization at pci_enable_device() time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int pcibios_plat_dev_init(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)  * If big-endian, enable hardware byteswap on the PCIe bridges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)  * This will make both the SoC and PCIe devices behave consistently with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)  * readl/writel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void xlp_config_pci_bswap(int node, int link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	uint64_t nbubase, lnkbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	nbubase = nlm_get_bridge_regbase(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	lnkbase = nlm_get_pcie_base(node, link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	 *  Enable byte swap in hardware. Program each link's PCIe SWAP regions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	 * from the link's address ranges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	if (cpu_is_xlp9xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		reg = nlm_read_bridge_reg(nbubase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 				BRIDGE_9XX_PCIEMEM_BASE0 + link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		nlm_write_pci_reg(lnkbase, PCIE_9XX_BYTE_SWAP_MEM_BASE, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		reg = nlm_read_bridge_reg(nbubase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 				BRIDGE_9XX_PCIEMEM_LIMIT0 + link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		nlm_write_pci_reg(lnkbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 				PCIE_9XX_BYTE_SWAP_MEM_LIM, reg | 0xfff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		reg = nlm_read_bridge_reg(nbubase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 				BRIDGE_9XX_PCIEIO_BASE0 + link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		nlm_write_pci_reg(lnkbase, PCIE_9XX_BYTE_SWAP_IO_BASE, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		reg = nlm_read_bridge_reg(nbubase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 				BRIDGE_9XX_PCIEIO_LIMIT0 + link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		nlm_write_pci_reg(lnkbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 				PCIE_9XX_BYTE_SWAP_IO_LIM, reg | 0xfff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_BASE0 + link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_BASE, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		reg = nlm_read_bridge_reg(nbubase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 					BRIDGE_PCIEMEM_LIMIT0 + link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_LIM, reg | 0xfff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_BASE0 + link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_BASE, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_LIMIT0 + link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Swap configuration not needed in little-endian mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static inline void xlp_config_pci_bswap(int node, int link) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #endif /* __BIG_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int __init pcibios_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	uint64_t pciebase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	int link, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	/* Firmware assigns PCI resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	pci_set_flags(PCI_PROBE_ONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	/* Extend IO port for memory mapped io */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	ioport_resource.start =	 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	ioport_resource.end   = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	for (n = 0; n < NLM_NR_NODES; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		if (!nlm_node_present(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		for (link = 0; link < PCIE_NLINKS; link++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 			pciebase = nlm_get_pcie_base(n, link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 			if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			xlp_config_pci_bswap(n, link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			xlp_init_node_msi_irqs(n, link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			/* put in intpin and irq - u-boot does not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 			reg = nlm_read_pci_reg(pciebase, 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 			reg &= ~0x1ffu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 			reg |= (1 << 8) | PIC_PCIE_LINK_LEGACY_IRQ(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 			nlm_write_pci_reg(pciebase, 0xf, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			pr_info("XLP PCIe: Link %d-%d initialized.\n", n, link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	set_io_port_base(CKSEG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	nlm_pci_controller.io_map_base = CKSEG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	register_pci_controller(&nlm_pci_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	pr_info("XLP PCIe Controller %pR%pR.\n", &nlm_pci_io_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		&nlm_pci_mem_resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) arch_initcall(pcibios_init);