^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pci-vr41xx.h, Include file for PCI Control Unit of the NEC VR4100 series.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2002 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Yoichi Yuasa <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __PCI_VR41XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __PCI_VR41XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PCIU_BASE 0x0f000c00UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PCIU_SIZE 0x200UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PCIMMAW1REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PCIMMAW2REG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PCITAW1REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PCITAW2REG 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PCIMIOAWREG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IBA(addr) ((addr) & 0xff000000U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MASTER_MSK(mask) (((mask) >> 11) & 0x000fe000U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PCIA(addr) (((addr) >> 24) & 0x000000ffU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TARGET_MSK(mask) (((mask) >> 8) & 0x000fe000U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ITA(addr) (((addr) >> 24) & 0x000000ffU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCIIA(addr) (((addr) >> 24) & 0x000000ffU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define WINEN 0x1000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PCICONFDREG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCICONFAREG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PCIMAILREG 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BUSERRADREG 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define EA(reg) ((reg) &0xfffffffc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define INTCNTSTAREG 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MABTCLR 0x80000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TRDYCLR 0x40000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PARCLR 0x20000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MBCLR 0x10000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SERRCLR 0x08000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RTYCLR 0x04000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MABCLR 0x02000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TABCLR 0x01000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* RFU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MABTMSK 0x00008000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TRDYMSK 0x00004000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PARMSK 0x00002000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MBMSK 0x00001000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SERRMSK 0x00000800U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RTYMSK 0x00000400U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MABMSK 0x00000200U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TABMSK 0x00000100U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IBAMABT 0x00000080U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TRDYRCH 0x00000040U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PAR 0x00000020U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MB 0x00000010U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PCISERR 0x00000008U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RTYRCH 0x00000004U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MABORT 0x00000002U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TABORT 0x00000001U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PCIEXACCREG 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define UNLOCK 0x2U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define EAREQ 0x1U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PCIRECONTREG 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RTRYCNT(reg) ((reg) & 0x000000ffU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PCIENREG 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PCIU_CONFIG_DONE 0x4U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PCICLKSELREG 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define EQUAL_VTCLOCK 0x2U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define HALF_VTCLOCK 0x0U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ONE_THIRD_VTCLOCK 0x3U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define QUARTER_VTCLOCK 0x1U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PCITRDYVREG 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TRDYV(val) ((uint32_t)(val) & 0xffU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PCICLKRUNREG 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define VENDORIDREG 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DEVICEIDREG 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define COMMANDREG 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define STATUSREG 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define REVIDREG 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CLASSREG 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CACHELSREG 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define LATTIMEREG 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MLTIM(val) (((uint32_t)(val) << 7) & 0xff00U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MAILBAREG 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PCIMBA1REG 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PCIMBA2REG 0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MBADD(base) ((base) & 0xfffff800U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PMBA(base) ((base) & 0xffe00000U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PREF 0x8U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PREF_APPROVAL 0x8U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PREF_DISAPPROVAL 0x0U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TYPE 0x6U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TYPE_32BITSPACE 0x0U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MSI 0x1U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MSI_MEMORY 0x0U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define INTLINEREG 0x13c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define INTPINREG 0x13c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RETVALREG 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PCIAPCNTREG 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TKYGNT 0x04000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TKYGNT_ENABLE 0x04000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TKYGNT_DISABLE 0x00000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PAPC 0x03000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PAPC_ALTERNATE_B 0x02000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PAPC_ALTERNATE_0 0x01000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PAPC_FAIR 0x00000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RTYVAL(val) (((uint32_t)(val) << 7) & 0xff00U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RTYVAL_MASK 0xff00U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PCI_CLOCK_MAX 33333333U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Default setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PCI_MASTER_MEM1_BUS_BASE_ADDRESS 0x10000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PCI_MASTER_MEM1_ADDRESS_MASK 0x7c000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PCI_MASTER_MEM1_PCI_BASE_ADDRESS 0x10000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PCI_TARGET_MEM1_ADDRESS_MASK 0x08000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PCI_TARGET_MEM1_BUS_BASE_ADDRESS 0x00000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PCI_MASTER_IO_BUS_BASE_ADDRESS 0x16000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PCI_MASTER_IO_ADDRESS_MASK 0x7e000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PCI_MASTER_IO_PCI_BASE_ADDRESS 0x00000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PCI_MAILBOX_BASE_ADDRESS 0x00000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PCI_TARGET_WINDOW1_BASE_ADDRESS 0x00000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IO_PORT_BASE KSEG1ADDR(PCI_MASTER_IO_BUS_BASE_ADDRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IO_PORT_RESOURCE_START PCI_MASTER_IO_PCI_BASE_ADDRESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IO_PORT_RESOURCE_END (~PCI_MASTER_IO_ADDRESS_MASK & PCI_MASTER_ADDRESS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PCI_IO_RESOURCE_START 0x01000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PCI_IO_RESOURCE_END 0x01ffffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PCI_MEM_RESOURCE_START 0x11000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PCI_MEM_RESOURCE_END 0x13ffffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #endif /* __PCI_VR41XX_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags