^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pci-vr41xx.c, PCI Control Unit routines for the NEC VR4100 series.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2001-2003 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Yoichi Yuasa <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2004-2008 Yoichi Yuasa <yuasa@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Changes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * MontaVista Software Inc. <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * - New creation, NEC VR4122 and VR4131 are supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/vr41xx/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/vr41xx/vr41xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "pci-vr41xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) extern struct pci_ops vr41xx_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static void __iomem *pciu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define pciu_read(offset) readl(pciu_base + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define pciu_write(offset, value) writel((value), pciu_base + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static struct pci_master_address_conversion pci_master_memory1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .bus_base_address = PCI_MASTER_MEM1_BUS_BASE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .address_mask = PCI_MASTER_MEM1_ADDRESS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .pci_base_address = PCI_MASTER_MEM1_PCI_BASE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static struct pci_target_address_conversion pci_target_memory1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .address_mask = PCI_TARGET_MEM1_ADDRESS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .bus_base_address = PCI_TARGET_MEM1_BUS_BASE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static struct pci_master_address_conversion pci_master_io = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .bus_base_address = PCI_MASTER_IO_BUS_BASE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .address_mask = PCI_MASTER_IO_ADDRESS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .pci_base_address = PCI_MASTER_IO_PCI_BASE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static struct pci_mailbox_address pci_mailbox = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .base_address = PCI_MAILBOX_BASE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static struct pci_target_address_window pci_target_window1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .base_address = PCI_TARGET_WINDOW1_BASE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct resource pci_mem_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .name = "PCI Memory resources",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .start = PCI_MEM_RESOURCE_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .end = PCI_MEM_RESOURCE_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct resource pci_io_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .name = "PCI I/O resources",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .start = PCI_IO_RESOURCE_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .end = PCI_IO_RESOURCE_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .master_memory1 = &pci_master_memory1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .target_memory1 = &pci_target_memory1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .master_io = &pci_master_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .exclusive_access = CANNOT_LOCK_FROM_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .wait_time_limit_from_irdy_to_trdy = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .mailbox = &pci_mailbox,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .target_window1 = &pci_target_window1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .master_latency_timer = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .retry_limit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .arbiter_priority_control = PCI_ARBITRATION_MODE_FAIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .take_away_gnt_mode = PCI_TAKE_AWAY_GNT_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct pci_controller vr41xx_pci_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .pci_ops = &vr41xx_pci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .mem_resource = &pci_mem_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .io_resource = &pci_io_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) void __init vr41xx_pciu_setup(struct pci_controller_unit_setup *setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) vr41xx_pci_controller_unit_setup = *setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int __init vr41xx_pciu_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct pci_controller_unit_setup *setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct pci_master_address_conversion *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct pci_target_address_conversion *target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct pci_mailbox_address *mailbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct pci_target_address_window *window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned long vtclock, pci_clock_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) setup = &vr41xx_pci_controller_unit_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (request_mem_region(PCIU_BASE, PCIU_SIZE, "PCIU") == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pciu_base = ioremap(PCIU_BASE, PCIU_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (pciu_base == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) release_mem_region(PCIU_BASE, PCIU_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Disable PCI interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) vr41xx_disable_pciint();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Supply VTClock to PCIU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) vr41xx_supply_clock(PCIU_CLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Dummy write, waiting for supply of VTClock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) vr41xx_disable_pciint();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Select PCI clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (setup->pci_clock_max != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) pci_clock_max = setup->pci_clock_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pci_clock_max = PCI_CLOCK_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) vtclock = vr41xx_get_vtclock_frequency();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (vtclock < pci_clock_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pciu_write(PCICLKSELREG, EQUAL_VTCLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) else if ((vtclock / 2) < pci_clock_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) pciu_write(PCICLKSELREG, HALF_VTCLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) else if (current_cpu_data.processor_id >= PRID_VR4131_REV2_1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) (vtclock / 3) < pci_clock_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pciu_write(PCICLKSELREG, ONE_THIRD_VTCLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) else if ((vtclock / 4) < pci_clock_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pciu_write(PCICLKSELREG, QUARTER_VTCLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) printk(KERN_ERR "PCI Clock is over 33MHz.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) iounmap(pciu_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Supply PCI clock by PCI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) vr41xx_supply_clock(PCI_CLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (setup->master_memory1 != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) master = setup->master_memory1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) val = IBA(master->bus_base_address) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MASTER_MSK(master->address_mask) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) WINEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PCIA(master->pci_base_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) pciu_write(PCIMMAW1REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) val = pciu_read(PCIMMAW1REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) val &= ~WINEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) pciu_write(PCIMMAW1REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (setup->master_memory2 != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) master = setup->master_memory2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) val = IBA(master->bus_base_address) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MASTER_MSK(master->address_mask) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) WINEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PCIA(master->pci_base_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) pciu_write(PCIMMAW2REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) val = pciu_read(PCIMMAW2REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) val &= ~WINEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) pciu_write(PCIMMAW2REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (setup->target_memory1 != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) target = setup->target_memory1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) val = TARGET_MSK(target->address_mask) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) WINEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ITA(target->bus_base_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pciu_write(PCITAW1REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) val = pciu_read(PCITAW1REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) val &= ~WINEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) pciu_write(PCITAW1REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (setup->target_memory2 != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) target = setup->target_memory2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) val = TARGET_MSK(target->address_mask) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) WINEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ITA(target->bus_base_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) pciu_write(PCITAW2REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) val = pciu_read(PCITAW2REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) val &= ~WINEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pciu_write(PCITAW2REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (setup->master_io != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) master = setup->master_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) val = IBA(master->bus_base_address) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MASTER_MSK(master->address_mask) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) WINEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PCIIA(master->pci_base_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pciu_write(PCIMIOAWREG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) val = pciu_read(PCIMIOAWREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) val &= ~WINEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pciu_write(PCIMIOAWREG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (setup->exclusive_access == CANNOT_LOCK_FROM_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) pciu_write(PCIEXACCREG, UNLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) pciu_write(PCIEXACCREG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (current_cpu_type() == CPU_VR4122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pciu_write(PCITRDYVREG, TRDYV(setup->wait_time_limit_from_irdy_to_trdy));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) pciu_write(LATTIMEREG, MLTIM(setup->master_latency_timer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (setup->mailbox != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) mailbox = setup->mailbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) val = MBADD(mailbox->base_address) | TYPE_32BITSPACE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MSI_MEMORY | PREF_APPROVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) pciu_write(MAILBAREG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (setup->target_window1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) window = setup->target_window1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) val = PMBA(window->base_address) | TYPE_32BITSPACE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MSI_MEMORY | PREF_APPROVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) pciu_write(PCIMBA1REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (setup->target_window2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) window = setup->target_window2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) val = PMBA(window->base_address) | TYPE_32BITSPACE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MSI_MEMORY | PREF_APPROVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) pciu_write(PCIMBA2REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) val = pciu_read(RETVALREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) val &= ~RTYVAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) val |= RTYVAL(setup->retry_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) pciu_write(RETVALREG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) val = pciu_read(PCIAPCNTREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) val &= ~(TKYGNT | PAPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) switch (setup->arbiter_priority_control) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case PCI_ARBITRATION_MODE_ALTERNATE_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) val |= PAPC_ALTERNATE_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case PCI_ARBITRATION_MODE_ALTERNATE_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) val |= PAPC_ALTERNATE_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) val |= PAPC_FAIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (setup->take_away_gnt_mode == PCI_TAKE_AWAY_GNT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) val |= TKYGNT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) pciu_write(PCIAPCNTREG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) pciu_write(COMMANDREG, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PCI_COMMAND_MASTER | PCI_COMMAND_PARITY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PCI_COMMAND_SERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Clear bus error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) pciu_read(BUSERRADREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) pciu_write(PCIENREG, PCIU_CONFIG_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (setup->mem_resource != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) vr41xx_pci_controller.mem_resource = setup->mem_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (setup->io_resource != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) vr41xx_pci_controller.io_resource = setup->io_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) set_io_port_base(IO_PORT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ioport_resource.start = IO_PORT_RESOURCE_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ioport_resource.end = IO_PORT_RESOURCE_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (setup->master_io) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) void __iomem *io_map_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct resource *res = vr41xx_pci_controller.io_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) master = setup->master_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) io_map_base = ioremap(master->bus_base_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (!io_map_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) vr41xx_pci_controller.io_map_base = (unsigned long)io_map_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) register_pci_controller(&vr41xx_pci_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) arch_initcall(vr41xx_pciu_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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