^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Based on linux/arch/mips/txx9/rbtx4939/setup.c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * and RBTX49xx patch from CELF patch archive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2001, 2003-2005 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/txx9/generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/txx9/tx4939.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) int __init tx4939_report_pciclk(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) int pciclk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) pr_info("PCIC --%s PCICLK:",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) (__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCI66) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) " PCI66" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) if (__raw_readq(&tx4939_ccfgptr->pcfg) & TX4939_PCFG_PCICLKEN_ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) pciclk = txx9_master_clock * 20 / 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) if (!(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCI66))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) pciclk /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) pr_cont("Internal(%u.%uMHz)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) (pciclk + 50000) / 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ((pciclk + 50000) / 100000) % 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) pr_cont("External");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) pciclk = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) pr_cont("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return pciclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void __init tx4939_report_pci1clk(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned int pciclk = txx9_master_clock * 20 / 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) pr_info("PCIC1 -- PCICLK:%u.%uMHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) (pciclk + 50000) / 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ((pciclk + 50000) / 100000) % 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4939_pcic1ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) switch (slot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) case TX4927_PCIC_IDSEL_AD_TO_SLOT(31):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (__raw_readq(&tx4939_ccfgptr->pcfg) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) TX4939_PCFG_ET0MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return TXX9_IRQ_BASE + TX4939_IR_ETH(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) case TX4927_PCIC_IDSEL_AD_TO_SLOT(30):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (__raw_readq(&tx4939_ccfgptr->pcfg) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) TX4939_PCFG_ET1MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return TXX9_IRQ_BASE + TX4939_IR_ETH(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int irq = tx4939_pcic1_map_irq(dev, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) irq = pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* IRQ rotation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) irq--; /* 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) irq = (irq + 33 - slot) % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) irq++; /* 1-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) switch (irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) irq = TXX9_IRQ_BASE + TX4939_IR_INTA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) irq = TXX9_IRQ_BASE + TX4939_IR_INTB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) irq = TXX9_IRQ_BASE + TX4939_IR_INTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) irq = TXX9_IRQ_BASE + TX4939_IR_INTD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) void __init tx4939_setup_pcierr_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (request_irq(TXX9_IRQ_BASE + TX4939_IR_PCIERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) tx4927_pcierr_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 0, "PCI error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) (void *)TX4939_PCIC_REG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) pr_warn("Failed to request irq for PCIERR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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