^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * and RBTX49xx patch from CELF patch archive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2001, 2003-2005 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/txx9/generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/txx9/tx4938.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) int __init tx4938_report_pciclk(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) int pciclk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) pr_info("PCIC --%s PCICLK:",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) " PCI66" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_PCICLKEN_ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) switch ((unsigned long)ccfg &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) TX4938_CCFG_PCIDIVMODE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) case TX4938_CCFG_PCIDIVMODE_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) pciclk = txx9_cpu_clock / 4; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) case TX4938_CCFG_PCIDIVMODE_4_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) pciclk = txx9_cpu_clock * 2 / 9; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) case TX4938_CCFG_PCIDIVMODE_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) pciclk = txx9_cpu_clock / 5; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) case TX4938_CCFG_PCIDIVMODE_5_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) pciclk = txx9_cpu_clock * 2 / 11; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) case TX4938_CCFG_PCIDIVMODE_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) pciclk = txx9_cpu_clock / 8; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) case TX4938_CCFG_PCIDIVMODE_9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) pciclk = txx9_cpu_clock / 9; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) case TX4938_CCFG_PCIDIVMODE_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) pciclk = txx9_cpu_clock / 10; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) case TX4938_CCFG_PCIDIVMODE_11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) pciclk = txx9_cpu_clock / 11; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) pr_cont("Internal(%u.%uMHz)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) (pciclk + 50000) / 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ((pciclk + 50000) / 100000) % 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) pr_cont("External");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) pciclk = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) pr_cont("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return pciclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) void __init tx4938_report_pci1clk(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int pciclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) txx9_gbus_clock / ((ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pr_info("PCIC1 -- %sPCICLK:%u.%uMHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) (ccfg & TX4938_CCFG_PCI1_66) ? "PCI66 " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) (pciclk + 50000) / 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ((pciclk + 50000) / 100000) % 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int __init tx4938_pciclk66_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int pciclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Assert M66EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) tx4938_ccfg_set(TX4938_CCFG_PCI66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Double PCICLK (if possible) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_PCICLKEN_ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int pcidivmode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pcidivmode = (unsigned long)ccfg &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) TX4938_CCFG_PCIDIVMODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) switch (pcidivmode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) case TX4938_CCFG_PCIDIVMODE_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) case TX4938_CCFG_PCIDIVMODE_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) pcidivmode = TX4938_CCFG_PCIDIVMODE_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pciclk = txx9_cpu_clock / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) case TX4938_CCFG_PCIDIVMODE_9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) case TX4938_CCFG_PCIDIVMODE_4_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) pciclk = txx9_cpu_clock * 2 / 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case TX4938_CCFG_PCIDIVMODE_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case TX4938_CCFG_PCIDIVMODE_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pcidivmode = TX4938_CCFG_PCIDIVMODE_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) pciclk = txx9_cpu_clock / 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case TX4938_CCFG_PCIDIVMODE_11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) case TX4938_CCFG_PCIDIVMODE_5_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) pciclk = txx9_cpu_clock * 2 / 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) tx4938_ccfg_change(TX4938_CCFG_PCIDIVMODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pcidivmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pr_debug("PCICLK: ccfg:%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) (unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pciclk = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return pciclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4938_pcic1ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) switch (slot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) case TX4927_PCIC_IDSEL_AD_TO_SLOT(31):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (__raw_readq(&tx4938_ccfgptr->pcfg) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) TX4938_PCFG_ETH0_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return TXX9_IRQ_BASE + TX4938_IR_ETH0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) case TX4927_PCIC_IDSEL_AD_TO_SLOT(30):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (__raw_readq(&tx4938_ccfgptr->pcfg) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) TX4938_PCFG_ETH1_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return TXX9_IRQ_BASE + TX4938_IR_ETH1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void __init tx4938_setup_pcierr_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (request_irq(TXX9_IRQ_BASE + TX4938_IR_PCIERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) tx4927_pcierr_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 0, "PCI error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) (void *)TX4927_PCIC_REG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pr_warn("Failed to request irq for PCIERR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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